Samsung S5PC100 User Manual page 639

S5PC100 USER'S MANUAL (REV1.0)
UCONn
Receive Mode
NOTE:
1. DIV_VAL = UBRDIVn + (num of 1's in UDIVSLOTn)/16. Refer to UART Buad Rate Configure Registers
2. RX interrupt type must be set to pulse for every transfer in S5PC100.
3. If the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA receive mode
with FIFO, the Rx interrupt is generated (receive time out), and you must check the FIFO status and read out
the rest.
4. When you want to change UCLK_CLK to PCLK for UART baudrate , clock selection field must be set to 2'b00.
But, when you want to change SCLK_UART to PCLK for UART baudrate , clock selection field must be set to 2'b10.
Bit
00 = Disable
01 = Interrupt request or polling mode
10 = DMA request( request signal 0)
11 = DMA request( request signal 1)
[1:0] This bit determines which function is able to read data from
UART receive buffer register.
00 = Disable
01 = Interrupt request or polling mode
10 = DMA request( request signal 0)
11 = DMA request( request signal 1)
Description
UART
Reset Value
00
8.1-15