Samsung S5PC100 User Manual page 8

S5PC100 USER'S MANUAL (REV1.0)
3.2 MEMORY SUBSYSTEM
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High bandwidth Memory Matrix subsystem
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Two independent external memory ports (1 x16 Static Hybrid Memory port and 1 x32 DRAM port)
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Matrix architecture increases overall bandwidth with the simultaneous access capability
♦ SRAM/ROM/NOR Interface
∗ x8 or x16 data bus
∗ Address range support: 21-bit
∗ Supports byte and half-word access
♦ NAND Interface
∗ Support industry standard NAND interface
∗ x8 data bus
∗ Density support: up to 32-Gb
♦ Muxed OneNAND Interface
∗ x16 data bus
∗ Supports byte and half-word access
∗ Supports 2KB page mode
∗ Supports FlexOneNAND (4KB page mode)
♦ Mobile DDR Interface
∗ x32 data bus with 333Mbps/pin double data rate (DDR)
∗ 1.8V interface voltage
∗ Density support: up to 1-Gb per 1 CS (support upto 2 CS)
♦ DDR2 Interface
∗ x32 data bus with 333Mbps/pin double data rate (DDR)
∗ 1.8V interface voltage
∗ Density support: up to 512Mb per 1 CS (support upto 2 CS, when 4bank DDR2)
∗ Density support: up to 4-Gb per 1 CS (support upto 1 CS, when 8 bank DDR2)
♦ Mobile PDDR2 interface
∗ x32 data bus with up to 333Mbps/pin
∗ 1.2V interface voltage
∗ Density support: up to 1-Gb per 1 CS (support upto 2 CS)
PRODUCT OVERVIEW
1.1-5