Port 0 Error Rate Enable Command And Status Register (P0Erecsr) - Freescale Semiconductor MSC8144E Reference Manual

Quad core media signal processor
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16.6.31 Port 0 Error Rate Enable Command and Status Register
(P0ERECSR)
P0ERECSR
Port 0 Error Rate Enable Command and Status Register
Bit
31
30
29
TYPE
RESET
0
0
0
Bit
15
14
13
TYPE
RESET
0
0
0
P0ERECSR contains the bits that control when an error condition is allowed to increment the
error rate counter in the port 0 error rate threshold register and lock the port 0 error capture
registers.
Bit
Reset
0
31–23
CCS
0
22
AUA
0
21
PNA
0
20
UA
0
19
CRC
0
18
EM
0
17
0
16–6
NOA
0
5
PE
0
4
0
3
DE
0
2
UCS
0
1
LTO
0
0
Freescale Semiconductor
28
27
26
25
0
0
0
0
12
11
10
9
0
0
0
0
Table 16-73. P0ERECSR Field Descriptions
Reserved. Write to zero for future compatibility.
CRC Control Symbol Enable
Enable error counting of a corrupt control symbol.
Acknowledge Control With Unexpected Acknowledge ID Enable
Enable error rate counting of an acknowledge control symbol with an unexpected
acknowledge ID.
Packet Not Accepted Enable
Enable error rate counting of packet-not-accepted acknowledge control symbols.
Unexpected Acknowledge ID Enable
Enable error rate counting of packets with an unexpected ackID value.
Bad CRC Enable
Enable error rate counting of packets with a bad CRC value.
Exceed Maximum Enable
Enable error rate counting of packets that exceed the maximum allowed size (276 bytes).
Reserved. Write to zero for future compatibility.
Not Outstanding Acknowledge
Enable error rate counting of ink-responses received with an acknowledge ID that is not
outstanding.
Protocol Error
Enable error rate counting of protocol errors.
Reserved. Write to zero for future compatibility.
Delineation Errors
Enable error rate counting of delineation errors.
Unsolicited Control Symbol
Enable error rate counting of unexpected acknowledge control symbols.
Link Time-Out
Enable error rate counting of an acknowledge or link-response control symbol not received
within the specified time-out interval.
MSC8144E Reference Manual, Rev. 3
24
23
22
21
CCS
AUA
PNA
R/W
0
0
0
0
8
7
6
5
NOA
R/W
0
0
0
0
Description
RapidIO Programming Model
Offset 0x00644
20
19
18
17
UA
CRC
EM
0
0
0
0
4
3
2
1
PE
DE
UCS
0
0
0
0
16
0
0
LTO
0
16-137

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