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Field
7,5,3,1
PWM channel n clock select. Selects between one of two clock sources for each PWM channel. See
PCLKn
"PWM Prescale Clock Select Register (PWMPRCLK)"
more information on how the different clock rates are generated. The even-numbered channels' clock select has no
effect when the corresponding PWMCTL[CONn(n+1)] bit is set. For example, if PWMCTL[CON01] equals 1,
PWMCLK[PCLK0] has no affect.
0
1
6,4,2,0
Reserved, must be cleared.
24.2.4
PWM Prescale Clock Select Register (PWMPRCLK)
The PWMPRCLK register selects the prescale clock source for clocks A and B independently. If the clock
prescale is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during
the transition.
Address: 0xFC09_0023 (PWMPRCLK)
7
R
0
W
Reset:
0
Figure 24-5. PWM Prescale Clock Select Register (PWMPRCLK)
Field
7
Reserved, must be cleared.
6–4
Clock B prescaler select. These three bits control the rate of Clock B, which can be used for PWM channels 3 and 7.
PCKB
Freescale Semiconductor
Table 24-4. PWMCLK Field Descriptions
PCLK7
PCLK5
(PCLK7 Clock
(PWM5 Clock
Source)
Source)
B
A
SB
SA
6
5
PCKB
0
0
Table 24-5. PWMPRCLK Field Descriptions
PCKB
000
001
...
111
MCF52277 Reference Manual, Rev. 1
Description
and
Section 24.2.7, "PWM Scale A Register (PWMSCLA)"
PCLK3
(PWM3 Clock
Source)
B
SB
4
3
0
0
0
Description
Clock B Rate
Internal bus clock ÷ 2
0
Internal bus clock ÷ 2
1
...
Internal bus clock ÷ 2
7
Pulse-Width Modulation (PWM) Module
Section 24.2.4,
PCLK1
(PWM1 Clock
Source)
A
SA
Access: User Read/Write
2
1
PCKA
0
0
for
0
0
24-5
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