Gpt Enable And Mode Select Register (Gmsn) - Freescale Semiconductor MCF5480 Reference Manual

11.3.1

GPT Enable and Mode Select Register (GMSn)

31 30 29
R
W
Reset 0 0
15 14 13
R WDE 0
N
W
Reset 0 0
Reg
Addr
Bits Name
31–24 OCPW
23–22 —
21–20 OCT
19–18 —
17–16 ICT
Freescale Semiconductor
28 27 26
OCPW
0 0 0 0
12 11 10
0 CE 0 SC
0 0 0 0
MBAR + 0x800 (GMS0), 0x810 (GMS1), 0x820 (GMS2), 0x830 (GSM3)
Figure 11-1. GPT Enable and Mode Select Register (GMSn)
Table 11-2. GMSn Field Descriptions
Output capture pulse width. Applies to OC pulse types only. This field specifies the number of clocks
(non-prescaled) to create a short output pulse at each output event. This pulse is generated at the
end of the output capture period and overlays the next OC period (rather than adding to the period).
This field is alternately used as the watchdog reset field if watchdog timer mode is enabled.
Reserved, should be cleared.
Output capture type. Describes action to occur at each output capture event, as follows:
00 Special case, output is immediately forced low without respect to each output capture event.
01 Output pulses highs, initial value is low (OCPW field applies).
10 Output pulses low, initial value is high (OCPW field applies).
11 Output toggles.
GPIO modalities can be used to achieve an initial output state prior to enabling OC mode. It is
important to move directly from GPIO output mode to OC mode and not to pass through the
TMS=000 state.
To prevent the internal timer mode from engaging during the GPIO state, CE bit should be cleared
during the configuration steps.
GPIO initialization is needed when presetting the I/O to 1 in conjunction with a simple toggle OCT
setting.
Reserved, should be cleared.
Input capture type. Describes the input transition type required to trigger an input capture event, as
follows:
00 Any input transition causes an IC event.
01 IC event occurs at input rising edge.
10 IC event occurs at input falling edge.
11 IC event occurs at any input pulse (i.e., at the second input edge).
MCF548x Reference Manual, Rev. 3
25 24 23 22
0 0
0 0 0 0
9 8 7 6
OD IEN 0 0
0 0 0 0
Description
Memory Map/Register Definition
21 20 19 18
OCT 0 0
0 0 0 0
5 4 3 2
GPIO 0
0 0 0 0
17 16
ICT
0 0
1 0
TMS
0 0
11-3