Current Link Descriptor Extended Address Registers (Eclndarn) - Freescale Semiconductor MSC8144E Reference Manual

17.3.5 Current Link Descriptor Extended Address Registers (ECLNDARn)

ECLNDAR0 Current Link Descriptor Extended Address Registers 0–3
ECLNDAR1
ECLNDAR2
ECLNDAR3
Bit 31 30 29
Type
Reset 0 0 0
Bit 15 14 13
Type
Reset 0 0 0
The ECLNDAR contains the extended address of the current link descriptor for the specified
channel.
Note: These registers are only used for RapidIO transactions. They are not used for accesses
to the internal RapidIO address space.
For RapidIO transactions in basic chaining mode, software must initialize this register and the
Current Link Descriptor Address Register (CLNDAR) to point to the first link descriptor in
memory. After the current descriptor is processed, the ECLNDAR and CLNDAR are loaded
from the Next Link Descriptor Extended Address Register (ENLNDAR) and the Next Link
Descriptor Address Register (NLNDAR). Then the controller evaluates the NLNDARn[EOLND]
field. If EOLND is cleared (0), the DMA controller reads in the new current link descriptor for
processing. If EOLND is set (1), the last descriptor of the list has completed. If extended chaining
mode is not enabled, all DMA transfers are complete and the DMA controller halts.
If extended chaining mode is enabled, the DMA controller examines the state of the EOLSD bit
in the next list descriptor address register (NLSDAR). If EOLSD is clear, the controller loads the
contents of the ENLSDAR into the Current List Descriptor Extended Address Register
(ECLSDAR) and the contents of the NLSDAR into the CLSDAR and reads the new list
descriptor from memory. If EOLSD is set, all DMA transfers are complete and the DMA
controller halts. Table 17-9 describes the ECLNDAR fields.
Bits Reset
—
0
31–4
ECLNDA 0
3–0
Freescale Semiconductor
28 27 26 25
0 0 0 0
12 11 10 9
—
0 0 0 0
Table 17-9. ECLNDAR Field Descriptions
Description
Reserved. Write to zero for future compatibility.
Current Link Descriptor Extended Address
Contains the most significant 4 bits of the 36-bit
address used with RapidIO transactions only.
Note: This field is not used for local
transactions.
MSC8144E Reference Manual, Rev. 3
Dedicated DMA Controller Programming Model
24 23 22 21
—
R/W
0 0 0 0
8 7 6 5
R/W
0 0 0 0
Offset 0x108
Offset 0x188
Offset 0x208
Offset 0x288
20 19 18 17
0 0 0 0
4 3 2 1
ECLNDA
0 0 0 0
Setting
17-25
16
0
0
0