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7.2.4 UARTi transmit register and UARTi transmit buffer register
Figure 7.2.5 shows the block diagram of transmit section; Figure 7.2.6 shows the structure of UARTi
transmit buffer register.
SP : Stop bit
PAR : Parity bit
2SP
SP
SP
PAR
1SP
Fig. 7.2.5 Block diagram of transmit section
(b15)
b7
Fig. 7.2.6 Structure of UARTi transmit buffer register
D
8
9-bit UART
Parity
enabled
UART
Parity
Clock sync.
7-bit UART
disabled
8-bit UART
Clock sync.
"0"
(b8)
b0
b7
7751 Group User's Manual
Data bus (odd)
Data bus (even)
Bit converter
D
D
D
D
D
7
6
5
4
8-bit UART
9-bit UART
Clock sync.
7-bit UART
UARTi transmit register
b0
UART0 transmit buffer register (Addresses 33
UART1 transmit buffer register (Addresses 3B
Bit
Transmit data is set.
8 to 0
15 to 9
Nothing is assigned.
SERIAL I/O
7.2 Block description
UARTi transmit
D
D
D
3
2
1
0
buffer register
16
16
Functions
Undefined
Undefined
TxD
i
, 32
)
16
, 3A
)
16
RW
At reset
WO
–
7–9
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