Maskable Interrupt Status Flag (Id); Program Status Word (Psw) - Renesas NU85E Preliminary User's Manual

8.3.5 Maskable interrupt status flag (ID)

This flag, which controls the operation status of maskable interrupts, stores information indicating whether the
acknowledgement of interrupt requests is enabled or disabled.
It is assigned to bit 5 of the program status word (PSW).
31
PSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Z
Bit position Bit name
5 ID
224
CHAPTER 8 INTC
Figure 8-11. Program Status Word (PSW)
Indicates whether maskable interrupt service is enabled or disabled.
0: The acknowledgement of maskable interrupts is enabled
1: The acknowledgement of maskable interrupts is disabled (pending)
This bit is set (1) by the DI instruction and cleared (0) by the EI instruction. Its value is also
rewritten by the RETI instruction or the LDSR instruction for the PSW.
Non-maskable interrupts and exceptions are acknowledged regardless of the status of this flag.
Also, when a maskable interrupt is acknowledged, the ID flag is automatically set (1).
An interrupt request that is generated while acknowledgement is disabled (ID = 1), is
acknowledged when the PIFn bit of the PICn register is set (1) and the ID flag is cleared (0) (n =
0 to 63).
Preliminary User's Manual A14874EJ3V0UM
8 7 6 5 4 3 2 1 0
Function
After reset
00000020H