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7.2.5 UARTi receive register and UARTi receive buffer register
Figure 7.2.7 shows the block diagram of receive section; Figure 7.2.8 shows the structure of UARTi receive
buffer register.
SP : Stop bit
PAR : Parity bit
RxD
i
SP
Fig. 7.2.7 Block diagram of receive section
(b15)
b7
Fig. 7.2.8 Structure of UARTi receive buffer register
0
0
0
0
0
Parity
enabled
2SP
UART
SP
PAR
Parity
1SP
Clock sync.
disabled
(b8)
b0
b7
7751 Group User's Manual
Data bus (odd)
Data bus (even)
0
0
D
D
D
8
7
6
8-bit UART
9-bit UART
9-bit UART
Clock sync.
7-bit UART
7-bit UART
8-bit UART
Clock sync.
b0
UART0 receive buffer register (Addresses 37
UART1 receive buffer register (Addresses 3F
Bit
Receive data is read out from here.
8 to 0
Nothing is assigned.
15 to 9
The value is "0" at reading.
SERIAL I/O
7.2 Block description
Bit converter
D
D
D
D
D
D
5
4
3
2
1
0
UARTi receive register
Functions
UARTi receive
buffer register
, 36
)
16
16
, 3E
)
16
16
RW
At reset
RO
Undefined
–
0
7–11
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