Dac Channel1 Data Output Register (Dac_Dor1); Dac Channel2 Data Output Register (Dac_Dor2) - ST STM32F102 Series Reference Manual

Digital-to-analog converter (DAC)
11.5.12

DAC channel1 Data Output Register (DAC_DOR1)

Address offset: 0x2C
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Reserved
Bits 31:12 Reserved.
DACC1DOR[11:0]: DAC channel1 data output
Bit 11:0
These bits are read only, they contain data output for DAC channel1.
11.5.13

DAC channel2 Data Output Register (DAC_DOR2)

Address offset: 0x30
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Reserved
Bits 31:12 Reserved.
DACC2DOR[11:0]: DAC channel2 data output
Bit 11:0
These bits are read only, they contain data output for DAC channel2.
204/690
27 26 25 24
Reserved
11 10 9 8
r r r r
27 26 25 24
Reserved
11 10 9 8
r r r r
23 22 21 20
7 6 5 4
DACC1DOR[11:0]
r r r r
23 22 21 20
7 6 5 4
DACC2DOR[11:0]
r r r r
RM0008
19 18 17 16
3 2 1 0
r r r r
19 18 17 16
3 2 1 0
r r r r