SCK1, ExSCK1
TxD1, ExTxD1
(transmit data)
RxD1, ExRxD1
(receive data)
Figure 22.18 SCI Input/Output Timing (Synchronous Mode)
φ
ADTRG
Figure 22.19 A/D Converter External Trigger Input Timing
φ
RESO
Rev. 1.00, 05/04, page 534 of 544
SCK1, ExSCK1
Figure 22.17 SCK Clock Input Timing
t
TXD
t
RESD
Figure 22.20 WDT Output Timing (RESO)
t
t
SCKW
SCKr
t
Scyc
t
t
RXS
RXH
t
TRGS
t
RESOW
t
SCKf
t
RESD