Cirrus Logic EP93 Series Manuals

Manuals and User Guides for Cirrus Logic EP93 Series. We have 1 Cirrus Logic EP93 Series manual available for free PDF download: User Manual

Cirrus Logic EP93 Series User Manual (825 pages)

ARM 9 Embedded Processor Family

Brand: Cirrus Logic | Category: Computer Hardware | Size: 7 MB

Table of Contents
3
Preface

23
Chapter 1. Introduction

29
Chapter 2. ARM920T Core and Advanced High-Speed Bus (AHB)

39
- Introduction
  
  39
- Overview: ARM920T Core
  
  39
  - Features
    39
  - Block Diagram
    40
  - Operations
    40
    
    Figure 2-1. ARM920T Block Diagram
    40
    
    ARM9TDMI Core
    41
    
    Memory Management Unit
    42
    
    Cache and Write Buffer
    43
  - Co-Processor Interface
    44
  - AMBA AHB Bus Interface Overview
    44
  - AHB Implementation Details
    45
  - Figure 2-2. Typical AMBA AHB System
    45
  - Figure 2-3. Main Data Paths
    46
  - Memory and Bus Access Errors
    47
  - Bus Arbitration
    47
    
    Main AHB Bus Arbiter
    48
    
    Table 2-1. AHB Arbiter Priority Scheme
    48
    
    EBI Bus Arbiter
    49
    
    SDRAM Slave Arbiter
    49
- AHB Decoder
  
  49
Chapter 3. Maverickcrunch Co-Processor

71
Chapter 4. Boot ROM

119
- Introduction
  
  119
  - Boot ROM Hardware Operational Overview
    119
    
    Memory Map
    119
  - Boot ROM Software Operational Overview
    119
    
    Boot Algorithm
    120
    
    Image Header
    120
    
    Flowchart
    121
- Boot Options
  
  122
  - Figure 4-1. Flow Chart of Boot ROM Software
    122
    
    Table 4-1. Boot Configuration Options
    123
    
    FLASH Boot
    124
    
    SPI Boot
    124
    
    UART Boot
    124
    
    Figure 4-2. Flow Chart of Boot Sequence for 16-Bit SDRAM Devices
    125
    
    SDRAM or Syncflash Boot
    125
    
    Synchronous Memory Operation
    125
Chapter 5. System Controller

127
- Introduction
  
  127
  - System Startup
    127
  - System Reset
    127
  - Hardware Configuration Control
    128
  - Table 5-1. Hardware Configuration Control Latched Pins
    128
  - Table 5-2. Boot Configuration Options
    129
  - Software System Configuration Options
    130
  - Clock Control
    130
    
    Figure 5-1. Phase Locked Loop (PLL) Structure
    130
    
    Oscillators and Programmable Plls
    130
    
    Bus and Peripheral Clock Generation
    131
    
    Figure 5-2. Clock Generation System
    132
    
    Figure 5-3. Bus Clock Generation
    133
    
    Table 5-3. Clock Speeds and Sources
    134
    
    Steps for Clock Configuration
    135
  - Power Management
    135
    
    Clock Gatings
    135
    
    System Power States
    136
    
    Table 5-4. Peripherals with PCLK Gating
    136
    
    Figure 5-4. Power States and Transitions
    137
  - Interrupt Generation
    138
- Registers
  
  139
Chapter 6. Vectored Interrupt Controller

164
- Interrupt Priority
  164
- Figure 6-1. Vectored Interrupt Controller Block Diagram
  164
- Interrupt Configuration
  165
- Table 6-1. Interrupt Configuration
  165
- Interrupt Details
  166
Chapter 7. Raster Engine with Analog/Lcd Integrated

169
- Table 6-2. VICX Register Summary
  170
Timing and Interface

183
- Introduction
  
  183
  - Table 7-1. Raster Engine Video Mode Output Examples
    184
- Features
  
  185
- Raster Engine Features Overview
  
  185
  - Hardware Blinking
    185
  - Color Look-Up Tables
    186
  - Grayscale/Color Generation for Monochrome/Passive Low Color Displays
    186
  - Frame Buffer Organization
    186
  - Table 7-2. Byte Oriented Frame Buffer Organization
    187
  - Frame Buffer Memory Size
    188
  - Pulse Width Modulated Brightness
    188
  - Hardware Cursor
    189
- Functional Details
  
  189
  - VILOSATI (Video Image Line Output Scanner and Transfer Interface)
    190
  - Figure 7-1. Raster Engine Block Diagram
    190
  - Video FIFO
    191
  - Figure 7-2. Video Buffer Diagram
    191
  - Video Pixel MUX
    192
  - Blink Function
    192
  - Color Look-Up-Tables
    193
  - Color RGB Mux
    193
  - Pixel Shift Logic
    194
  - Table 7-3. Output Pixel Transfer Modes
    195
  - Grayscale/Color Generator for Monochrome/Passive Low Color Displays
    197
    
    FRAME_CNT3, FRAME_CNT4 Counters
    198
    
    Frame_Cntx Timing
    198
    
    HORZ_CNT3, HORZ_CNT4 Counters
    198
    
    Horz_Cntx (Pixel) Timing
    198
    
    VERT_CNT3, VERT_CNT4 Counters
    198
    
    Vert_Cntx (Line) Timing
    198
    
    Grayscale Look-Up Table (Gryscllut)
    199
    
    Table 7-4. Grayscale Lookup Table (Gryscllut)
    199
    
    Gryscllut Timing Diagram
    200
    
    Table 7-5. Grayscale Timing Diagram
    200
    
    Table 7-6. Programming Format
    201
    
    Figure 7-3. Graphics Matrix for 50% Duty Cycle
    202
    
    Figure 7-4. Sample Matrix Causing Flickering
    203
    
    Figure 7-5
    203
    
    Figure 7-6. Programming for One-Third Luminous Intensity
    204
    
    Table 7-7. Programming 50% Duty Cycle into Lookup Table
    204
    
    Figure 7-7. Creating Bit Patterns that Move to the Right
    205
    
    Table 7-8. Programming 33% Duty Cycle into the Lookup Table
    205
  - Hardware Cursor
    206
    
    Figure 7-8. Three and Four Count Axis
    206
    
    Table 7-9. Programming 33% Duty Cycle into the Lookup Table
    206
    
    Table 7-10. Cursor Memory Organization
    207
    
    Registers Used for Cursor
    208
  - Video Timing
    210
    
    Figure 7-9. Progressive/Dual Scan Video Signals
    210
    
    Figure 7-10. Interlaced Video Signals
    212
    
    Setting the Video Memory Parameters
    213
    
    Pixelmode
    214
  - Blink Logic
    214
    
    Blinkrate
    214
    
    Defining Blink Pixels
    214
    
    Table 7-11. Bits P[2:0] in the Pixelmode Register
    214
    
    Types of Blinking
    215
  - Color Mode Definition
    217
    
    16-Bit 555 Color Definition Mode
    217
    
    16-Bit 565 Color Definition Mode
    217
    
    Pixel Look-Up Table Mode
    217
    
    Triple 8-Bit Color Definition Mode
    217
- Registers
  
  218
Chapter 8 . Graphics Accelerator

265
- Overview
  
  265
- Block Processing Modes
  
  265
  - Copy
    266
    
    Logical Destination
    266
    
    Logical Mask
    266
    
    Operation Precedence
    266
    
    Transparency
    266
  - Remapping
    267
  - Block Fills
    267
  - Packed Memory Transfer
    267
- Line Draws
  
  267
  - Breshenham Line Draws
    268
  - Pixel Step Line Draws
    268
- Memory Organization for Graphics Accelerator
  
  268
  - Table 8-1. Screen Pixels
    268
    
    Memory Organization for 1 Bit Per Pixel (Bpp)
    269
    
    Memory Organization for 4-Bits Per Pixel
    269
    
    Memory Organization for 8-Bits Per Pixel
    269
    
    Table 8-2. Bpp Memory Organization
    269
    
    Table 8-3. 4 Bpp Memory Organization
    269
    
    Memory Organization for 16-Bits Per Pixel
    270
    
    Table 8-4. 8 Bpp Memory Organization
    270
    
    Table 8-5. 16 Bpp Memory Organization
    270
    
    Memory Organization for 24-Bits Per Pixel
    271
    
    Table 8-6. 24 Bpp Packed Memory Organization (4 Pixel/ 3 Words)
    271
    
    Table 8-7. 24 Bpp Unpacked Memory Organization (1 Pixel/ 1 Word)
    271
    
    Memory Map Access
    272
- Register Programming
  
  272
  - Word Count
    272
    
    Example: 8 BPP Mode
    272
    
    Example: 24 BPP (Packed) Mode
    273
  - Pixel End and Start
    273
    
    Table 8-10. Transfer Example 3
    273
    
    Table 8-11. Transfer Example 4
    273
    
    Table 8-12. Transfer Example 5
    273
    
    Table 8-9. Transfer Example 2
    273
    
    BPP Word Layout
    274
    
    Table 8-13. 4 BPP Memory Layout for Source Image
    274
    
    Table 8-14. 4 BPP Memory Layout for Destination Image
    274
    
    BPP WORD Layout
    275
    
    Table 8-15. 8 BPP Memory Layout for Source Image
    275
    
    Table 8-16. 8 BPP Memory Layout for Destination Image
    275
    
    Table 8-17. 16 BPP Memory Layout for Source Image
    275
    
    BPP Mode
    276
    
    Table 8-18. 16 BPP Memory Layout for Destination Image
    276
    
    Table 8-19. 24 BPP Memory Layout for Source Image
    276
- Register Usage
  
  277
- Registers
  
  286
  - Table 8-22. Graphics Accelerator Registers
    286
  - Table 8-23. Pixel Mode Encoding
    294
Chapter 9 . 1/10/100 Mbps Ethernet LAN Controller

303
- Introduction
  
  303
  - Detailed Description
    303
    
    Figure 9-1. 1/10/100 Mbps Ethernet LAN Controller Block Diagram
    303
    
    Host Interface and Descriptor Processor
    303
    
    Address Space
    304
    
    Power-Down Modes
    304
    
    Reset and Initialization
    304
  - MAC Engine
    305
    
    Data Encapsulation
    305
    
    Table 9-1. FIFO RAM Address Map
    305
    
    Figure 9-2. Ethernet Frame / Packet Format (Type II Only)
    306
  - Packet Transmission Process
    307
    
    Carrier Deference
    307
    
    Figure 9-3. Packet Transmission Process
    307
    
    Figure 9-4. Carrier Deference State Diagram
    308
  - Transmit Back-Off
    309
    
    The FCS Field
    309
    
    Transmission
    309
    
    Bit Order
    310
    
    Destination Address (DA) Filter
    310
    
    Figure 9-5. Data Bit Transmission Order
    310
    
    Perfect Address Filtering
    310
    
    Figure 9-6. CRC Logic
    311
    
    Hash Filter
    311
    
    Flow Control
    312
    
    Receive Flow Control
    312
    
    Table 9-2. Rxctl.ma and Rxctl.iaha[0] Relationships
    312
    
    Transmit Flow Control
    312
    
    Accessing the MII
    313
    
    Rx Missed and Tx Collision Counters
    313
- Descriptor Processor
  
  315
  - Receive Descriptor Processor Queues
    315
  - Receive Descriptor Queue
    315
  - Figure 9-7. Receive Descriptor Format and Data Fragments
    316
  - Receive Status Queue
    318
    
    Figure 9-8. Receive Status Queue
    319
    
    Receive Status Format
    320
    
    Figure 9-9. Receive Flow Diagram
    323
    
    Receive Flow
    323
    
    Receive Errors
    324
    
    Figure 9-10. Receive Descriptor Data/Status Flow
    325
    
    Receive Descriptor Data/Status Flow
    325
    
    Figure 9-11. Receive Descriptor Example
    326
    
    Receive Descriptor Example
    326
    
    Figure 9-12. Receive Frame Pre-Processing
    327
    
    Receive Frame Pre-Processing
    327
    
    Transmit Descriptor Processor Queues
    328
    
    Transmit Descriptor Queue
    328
    
    Figure 9-13. Transmit Descriptor Format and Data Fragments
    329
    
    Figure 9-14. Multiple Fragments Per Transmit Frame
    330
    
    Transmit Descriptor Format
    330
    
    Transmit Status Queue
    332
    
    Figure 9-15. Transmit Status Queue
    333
    
    Transmit Status Format
    334
    
    Figure 9-16. Transmit Flow Diagram
    336
    
    Transmit Flow
    336
    
    Transmit Errors
    337
    
    Figure 9-17. Transmit Descriptor Data/Status Flow
    338
    
    Transmit Descriptor Data/Status Flow
    338
  - Interrupts
    339
    
    Interrupt Processing
    339
  - Initialization
    339
    
    Interrupt Processing
    340
    
    Other Processing
    340
    
    Receive Queue Processing
    340
    
    Transmit Queue Processing
    340
    
    Transmit Restart Process
    341
- Registers
  
  342
Chapter 10 . DMA Controller

395
- Introduction
  
  395
- Registers
  
  414
Chapter 11. Universal Serial Bus Host Controller

441
- Introduction
  
  441
  - Features
    441
- Overview
  
  441
  - Data Transfer Types
    442
  - Figure 11-1. USB Focus Areas
    442
  - Host Controller Interface
    443
    
    Communication Channels
    443
    
    Figure 11-2. Communication Channels
    443
    
    Data Structures
    444
    
    Figure 11-3. Typical List Structure
    444
    
    Figure 11-4. Interrupt Endpoint Descriptor Structure
    445
  - Host Controller Driver Responsibilities
    446
    
    Bandwidth Allocation
    446
    
    Figure 11-5. Sample Interrupt Endpoint Schedule
    446
    
    Host Controller Management
    446
    
    List Management
    447
    
    Root Hub
    447
    
    Table 11-1. Frame Bandwidth Allocation
    447
  - Host Controller Responsibilities
    448
    
    Frame Management
    448
    
    List Processing
    448
    
    USB States
    448
  - USB Host Controller Blocks
    449
    
    AHB Master
    449
    
    AHB Slave
    449
    
    Figure 11-6. USB Host Controller Block Diagram
    449
    
    HCI Slave Block
    449
    
    Data FIFO
    450
    
    HCI Master Block
    450
    
    List Processor
    450
    
    Root Hub and Host SIE
    450
    
    USB State Control
    450
- Registers
  
  451
  - Table 11-2. Openhci Register Addresses
    451
Chapter 12. Static Memory Controller

479
Chapter 13. SDRAM, Syncrom, and Syncflash Controller

497
Chapter 14. UART1 with HDLC and Modem Control Signals

523
- Introduction
  
  523
- UART Overview
  
  523
  - UART Functional Description
    524
    
    AMBA APB Interface
    524
    
    DMA Block
    524
    
    Register Block
    524
    
    Figure 14-1. UART Block Diagram
    525
    
    Baud Rate Generator
    526
    
    Interrupt Generation Logic
    526
    
    Receive FIFO
    526
    
    Receive Logic
    526
    
    Transmit FIFO
    526
    
    Transmit Logic
    526
    
    Synchronizing Registers and Logic
    527
    
    UART Operation
    527
    
    Disabling the Fifos
    528
    
    Error Bits
    528
    
    Figure 14-2. UART Character Frame
    528
    
    Figure 14-3. UART Character Frame
    528
    
    System/Diagnostic Loopback Testing
    528
    
    Table 14-1. Receive FIFO Bit Functions
    528
    
    UART Character Frame
    528
    
    Interrupts
    529
    
    Uartmsintr
    529
    
    Uartrxintr
    529
    
    Uarttxintr
    529
    
    Uartintr
    530
    
    Uartrtintr
    530
  - Modem
    530
  - Hdlc
    530
    
    Overview of HDLC Modes
    531
    
    Selecting HDLC Modes
    531
    
    Table 14-2. Legal HDLC Mode Configurations
    532
    
    HDLC Receive
    533
    
    HDLC Transmit
    533
    
    Address Matching
    534
    
    Crcs
    534
    
    Aborts
    535
    
    Table 14-3. HDLC Receive Address Matching Modes
    535
    
    Dma
    536
    
    Writing Configuration Registers
    536
  - UART1 Package Dependency
    536
    
    Clocking Requirements
    537
    
    Table 14-4. UART1 Pin Functionality
    537
    
    Table 14-5. Devicecfg Register Bit Functions
    537
    
    Bus Bandwidth Requirements
    538
- Registers
  
  539
Chapter 15 . UART2

559
- Introduction
  559
- Irda SIR Block
  559
  - Irda SIR Encoder/Decoder Functional Description
    559
    
    Figure 15-1. Irda SIR Encoder/Decoder Block Diagram
    560
    
    Irda SIR Receive Decoder
    560
    
    Irda SIR Transmit Encoder
    560
    
    Irda SIR Operation
    561
    
    Figure 15-2. Irda Data Modulation (3/16)
    562
    
    Irda Data Modulation
    562
    
    System/Diagnostic Loopback Testing
    562
    
    Enabling Infrared (Ir) Modes
    563
  - UART2 Package Dependency
    563
    
    Clocking Requirements
    563
    
    Table 15-1. UART2 / Irda Modes
    563
    
    Table 15-2. Ionu2 Pin Function
    563
    
    Bus Bandwidth Requirements
    564
  - Registers
    565
Chapter 16 . UART3 with HDLC Encoder

577
- Introduction
  577
- Implementation Details
  577
  - UART3 Package Dependency
    577
  - Table 16-1. UART3 Pin Functionality
    577
  - Clocking Requirements
    578
  - Bus Bandwidth Requirements
    578
  - Table 16-2. Devicecfg Register Bit Functions
    578
  - Registers
    579
Chapter 17 . Irda

597
- Introduction
  597
- Shared Irda Interface Feature
  598
  - Overview
    598
  - Functional Description
    598
    
    General Configuration
    599
    
    Table 17-1. Bit Values to Select Ir Module
    599
    
    Transmitting Data
    599
    
    Receiving Data
    601
    
    Table 17-2. Address Offsets for End-Of-Frame Data
    601
    
    Special Conditions
    603
    
    Control Information Buffering
    604
  - Medium Irda Specific Features
    604
    
    Bit Encoding
    604
    
    Introduction
    604
    
    Figure 17-1. RZ1/NRZ Bit Encoding Example
    605
    
    Frame Format
    605
    
    Table 17-3. mir Frame Format
    605
    
    Baud Rate Generation
    607
    
    Functional Description
    607
    
    Receive Operation
    607
    
    Transmit Operation
    609
  - Fast Irda Specific Features
    609
    
    4PPM Modulation
    610
    
    Figure 17-2. 4PPM Modulation Encoding
    610
    
    Introduction
    610
    
    Figure 17-3. 4PPM Modulation Example
    611
    
    Figure 17-4. Irda (4.0 Mbps) Transmission Format
    611
    
    Mbps FIR Frame Format
    611
    
    Baud Rate Generation
    613
    
    Functional Description
    613
    
    Receive Operation
    614
    
    Transmit Operation
    615
    
    Irda Connectivity
    616
    
    Table 17-4. Devicecfg.ionu2 Pin Function
    616
    
    Clocking Requirements
    617
    
    Enabling Infrared Modes
    617
    
    Irda Integration Information
    617
    
    Table 17-5. UART2 / Irda Modes
    617
    
    Bus Bandwidth Requirements
    618
    
    Table 17-6. Irda Service Memory Accesses / Second
    618
  - Registers
    636
    
    Free Running Mode
    636
    
    Pre-Load Mode
    636
Chapter 18 . Timers

636
- 40-Bit Timer Operation
  636
- Table 18-1. Timers Register Map
  636
Chapter 19. Watchdog Timer

644
- Watchdog Activation
  644
- Clocking Requirements
  644
- Reset Requirements
  644
- Watchdog Status
  644
- Registers
  
  645
  - Table 19-1. Watchdog Timer Register Memory Map
    645
Chapter 20 . Real Time Clock with Software Trim

649
- Introduction
  649
  - Software Trim
    649
    
    Oscillator Frequency Calibration
    650
    
    Rtcswcomp Value Determination
    650
    
    Software Compensation
    650
    
    Example - Measured Value Split into Integer and Fractional Component
    651
    
    Maximum Error Calculation Vs. Real Time Clock Accuracy
    651
    
    Real-Time Interrupt
    651
    
    Reset Control
    652
- Registers
  
  652
Chapter 21 . I S Controller

661
- I 2 S Receiver Channel Overview
  661
  - Receiver Fifo's
    662
  - I 2 S Master Clock Generation
    663
    
    Table 21-4. I2Sclkdiv SYSCON Register Effect on I
    664
    
    Example of the Bit Clock Generation
    665
    
    I 2 S Bit Clock Rate Generation
    665
    
    Table 21-5. Bit Clock Rate Generation
    665
    
    Example of Right Justified LRCK Format
    666
  - Interrupts
    666
  - Figure 21-2. Bit Clock Generation Example
    666
  - Figure 21-3. Frame Format for Right Justified Data
    666
  - Registers
    668
    
    S TX Registers
    668
    
    Table 21-6. FIFO Flags
    668
    
    I 2 S RX Registers
    675
    
    Table 21-8. I 2 S RX Registers
    675
    
    I 2 S Configuration and Status Registers
    681
    
    Table 21-9. I 2 S Configuration and Status Registers
    681
    
    I 2 S Global Status Registers
    685
    
    Table 22-1. AC'97 Input and Output Signals
    689
Chapter 22. AC'97 Controller

690
- Interrupts
  691
  - Channel Interrupts
    691
    
    Ris
    691
    
    Tis
    691
    
    Codecready
    692
    
    Global Interrupts
    692
    
    Gpioint
    692
    
    Rtis
    692
    
    Tcis
    692
    
    Wint
    692
    
    Gpiotxcomplete
    693
    
    Slot1Txcomplete
    693
    
    Slot2Int
    693
    
    Slot2Txcomplete
    693
  - System Loopback Testing
    693
  - Registers
    693
  - Table 22-2. AC'97 Register Memory Map
    693
  - Table 22-3. Interaction between RSIZE and CM
    697
  - Table 22-4. Interaction between RSIZE and CM Bits
    699
Chapter 23 . Synchronous Serial Port

713
Chapter 24 . Pulse Width Modulator

733
- Introduction
  
  733
  - Example
    734
  - Static Programming (PWM Is Not Running) Example
    734
  - Table 24-1. Static Programming Steps
    734
  - Dynamic Programming (PWM Is Running) Example
    735
  - Programming Rules
    735
- Registers
  
  735
  - Table 24-2. Dynamic Programming Steps
    735
  - Table 24-3. PWM Registers Map
    735
Chapter 25 . Analog Touch Screen Interface

739
- Introduction
  
  739
  - Table 25-1. Switch Definitions and Logical Safeguards to Prevent Physical Damage
    741
    
    Figure 25-2. 8-Wire Resistive Interface Switching Diagram
    743
    
    Figure 25-3. 4-Wire Analog Resistive Interface Switching Diagram
    744
    
    Table 25-2. Touch Screen Switch Register Configurations
    745
    
    Figure 25-4. Analog Resistive Touch Screen Scan Flow Chart
    747
    
    Five-Wire and Seven-Wire Operation
    748
    
    Figure 25-5. 5-Wire Analog Resistive Interface Switching Diagram
    749
    
    Direct Operation
    750
    
    Figure 25-6. 5-Wire Feedback (7-Wire) Analog Resistive Interface Switching Diagram
    750
    
    Figure 25-7. Power down Detect Press Switching Diagram
    751
    
    Measuring Analog Input with the Touch Screen Controls Disabled
    751
    
    Figure 25-8. Other Switching Diagrams
    752
    
    Figure 25-9. Measure Resistance Switching Diagram
    753
    
    Measuring Touch Screen Resistance
    753
    
    Polled and Interrupt-Driven Modes
    754
    
    Table 25-3. External Signal Functions
    754
    
    Touch Screen Package Dependency
    754
- Registers
  
  755
  - Table 25-4. Analog Touch Screen Register Memory Map
    755
Chapter 26 . Keypad Interface

763
- Introduction
  
  763
  - Figure 26-1. Key Array Block Diagram
    763
- Theory of Operation
  
  764
  - Apparent Key Detection
    765
  - Figure 26-2. 8 X 8 Key Array Diagram
    765
  - Figure 26-3. Apparent Key 00H
    766
  - Scan and Debounce
    767
  - Interrupt Generation
    767
  - Low Power Mode
    768
  - Three-Key Reset
    768
- Registers
  
  768
  - Table 26-1. Keypad Interface Register Memory Map
    768
Chapter 27 . IDE Interface

771
- Introduction
  771
- Theory of Operation
  771
  - Diagrams and State Machines
    772
  - Figure 27-1. IDE Interface Signal Connections
    772
  - Table 27-1. IDE Host to IDE Interface Definition
    772
  - PIO Operations
    773
  - MDMA Operations
    774
  - UDMA Operations
    775
  - Performance Considerations
    775
  - UDMA Example
    776
  - DMA Request Latency
    777
    
    DMA Request Deassertion
    777
    
    DMA Request Latency Overview
    777
    
    Table 27-2. IDE Cycle Times and Data Transfer Rates
    777
    
    IDE DMA Programming Considerations
    778
    
    Table 27-3. Wait State Value for the DMA M2M Register Control.pwsc
    778
    
    Table 27-4. HCLK Cycles to De-Assert DMA Request
    778
    
    Bus Bandwidth Requirements
    779
    
    IDE Package Dependency
    779
    
    System Configuration Constraints
    779
    
    Table 27-5. Maximum Theoretical Bandwidths for Various Operating Modes
    779
  - Registers
    780
  - Table 27-6. IDE Interface Register Map
    780
Chapter 28. GPIO Interface

791
- Introduction
  791
Chapter 29. Security

809
- Introduction
  809
- Features
  809
- Contact Information
  809
- Registers
  810
- Table 29-1. Security Register List
  810
Chapter 30. Glossary

811
- Table 30-1. Glossary
  811
Chapter 31. EP93XX Register List

813
- Table 31-1. Ep93Xx Register List
  813

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More Cirrus Logic Manuals

Cirrus Logic EP93 Series Manuals

Cirrus Logic EP93 Series User Manual (825 pages)

Table of Contents

Preface

About the Ep93Xx User's Guide

Related Documents from Cirrus Logic

Reference Documents

Notational Conventions

Register Example

Chapter 1. Introduction

Introduction

Ep93Xx Features

Ep93Xx Processor Applications

Ep93Xx Processor Highlights

Chapter 2. ARM920T Core and Advanced High-Speed Bus (AHB)

Introduction

Overview: ARM920T Core

AHB Decoder

Chapter 3. Maverickcrunch Co-Processor

Introduction

Programming Examples

DSPSC Register

ARM Co-Processor Instruction Format

Instruction Set for the Maverickcrunch Co-Processor

Chapter 4. Boot ROM

Introduction

Boot Options

Chapter 5. System Controller

Introduction

Registers

Chapter 6. Vectored Interrupt Controller

Chapter 7. Raster Engine with Analog/Lcd Integrated

Timing and Interface

Introduction

Features

Raster Engine Features Overview

Functional Details

Registers

Chapter 8 . Graphics Accelerator

Overview

Block Processing Modes

Line Draws

Memory Organization for Graphics Accelerator

Register Programming

Register Usage

Registers

Chapter 9 . 1/10/100 Mbps Ethernet LAN Controller

Introduction

Descriptor Processor

Registers

Chapter 10 . DMA Controller

Introduction

Registers

Chapter 11. Universal Serial Bus Host Controller

Introduction

Overview

Registers

Chapter 12. Static Memory Controller

Introduction

Static Memory Controller Operation

PCMCIA Interface (EP9315 Processor Only)

PC Card Memory-Mode Enable Signals

PC Card Memory Mapping

Registers

Chapter 13. SDRAM, Syncrom, and Syncflash Controller

Introduction

Booting from Syncrom or Syncflash

Address Pin Usage

SDRAM Initialization

Programming Mode Register: SDRAM or Syncrom Device

SDRAM Self Refresh

Programming Registers: Syncflash Device

External Synchronous Memory System

Registers

Chapter 14. UART1 with HDLC and Modem Control Signals

Introduction

UART Overview

Registers

Chapter 15 . UART2

Chapter 16 . UART3 with HDLC Encoder