2.5G/5G/10G Multi-Rate Ethernet Phy Ip Core - Intel Arria 10 User Manual

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
2.6.4.13. TimeQuest Timing Constraints
To pass timing analysis, you must decouple the clocks in different time domains. The
necessary Synopsys Design Constraints File (.sdc) timing constraints are included in
the top-level wrapper file.
2.6.5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core
2.6.5.1. About 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core
The 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP core implements the Ethernet
protocol as defined in Clause 36 of the IEEE 802.3 2005 Standard. The PHY IP core
consists of a physical coding sublayer (PCS) function and an embedded physical media
attachment (PMA). You can dynamically switch the PHY operating speed.
Figure 79. Block Diagram of the PHY IP Core
Intel Device with Serial Transceivers
LL Ethernet
10G MAC
User
Application
Legend
Related Information
• Using the Arria 10 Transceiver Native PHY IP Core
• Recommended Reset Sequence
• Low Latency Ethernet 10G MAC User Guide
Describes the Low Latency Ethernet 10G MAC IP Core.
2.6.5.1.1. Features
Table 151. PHY Features
Feature
Multiple operating speeds
MAC-side interface
1G/2.5G/5G/10G Multi-rate Ethernet PHY
TX
GMII / XGMII
Soft PCS
RX
GMII / XGMII
Configuration
Registers
Avalon-MM
Interface
Transceiver
Reconfiguration Block
Hard IP
Reset
Controller
Soft Logic
1G, 2.5G, 5G, and 10G.
16-bit GMII for 1G and 2.5G.
Native PHY Hard IP
Hard PCS PMA
TX
Serial Clock
PLL
for 1 GbE for 2.5 GbE
125-MHz
Reference Clock
on page 45
on page 418
Description
®
Intel
TX Serial
External
PHY
RX Serial
RX CDR
Reference
Clock
PLL PLL
for 10 GbE
322-MHz
Reference Clock
continued...
®
Arria 10 Transceiver PHY User Guide
199