Intel Arria 10 User Manual page 371

3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Table 241. CMU PLL—Dynamic Reconfiguration
Parameters
Enable dynamic reconfiguration
Enable Altera Debug Master
Endpoint
Separate reconfig_waitrequest
from the status of AVMM
arbitration with PreSICE
Enable capability registers
Set user-defined IP identifier
Enable control and status registers
Configuration file prefix
Generate SystemVerilog package
file
Generate C header file
Generate MIF (Memory Initialize
File)
Table 242. CMU PLL—Generation Options
Parameters
Generate parameter
documentation file
Table 243. CMU PLL IP Ports
Port
pll_powerdown
pll_refclk0
pll_refclk1
pll_refclk2
Range
On/Off Enables the PLL reconfiguration interface. Enables the
simulation models and adds more ports for reconfiguration.
On/Off When you turn this option On, the transceiver PLL IP core
includes an embedded Altera Debug Master Endpoint that
connects internally to the Avalon-MM slave interface for
dynamic reconfiguration. The ADME can access the
reconfiguration space of the transceiver. It can perform
certain test and debug functions via JTAG using the System
Console. Refer to the Reconfiguration Interface and
Dynamic Reconfiguration chapter for more details.
On/Off
When enabled, the
indicate the status of AVMM arbitration with PreSICE. The
AVMM arbitration status is reflected in a soft status register
bit. (Only available if "Enable control and status registers
feature" is enabled).
On/Off Enables capability registers that provide high- level
information about the CMU PLL's configuration.
Sets a user-defined numeric identifier that can be read from
the
user_identifier
are enabled.
On/Off Enables soft registers for reading status signals and writing
control signals on the PLL interface through the embedded
debug logic.
Enter the prefix name for the configuration files to be
generated.
On/Off Generates a SystemVerilog package file containing all
relevant parameters used by the PLL.
On/Off Generates a C header file containing all relevant parameters
used by the PLL.
On/Off Generates a MIF file that contains the current configuration.
Use this option for reconfiguration purposes in order to
switch between different PLL configurations.
Range
On/Off Generates a .csv file which contains the descriptions of all
CMU PLL parameters and values.
Range Clock Domain
input Asynchronous
input N/A
input N/A
input N/A
Description
does not
reconfig_waitrequest
offset when the capability registers
Description
Description
Resets the PLL when asserted high.
Reference clock input port 0.
There are 5 reference clock input
ports. The number of reference clock
ports available depends on the
Number of PLL reference clocks
parameter.
Reference clock input port 1.
Reference clock input port 2.
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Intel Arria 10 Transceiver PHY User Guide
371