Intel Arria 10 User Manual page 185

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Word Bit R/W
Addr
30:28 RW
0x4C4 31:0 RW
0x4C5 15:0 RW
0x4C6 31:0 RW
0x4C7 15:0 RO
0x4C8 31:0 RO
0x4C9 15:0 RO
0x4CA 31:0 RO
0x4CB 24:0 RO
Name
AN_PAUSE value to override. The following bits are defined:
Override
•
AN_PAUSE[2:0]
•
•
You must set 0xC0 bit-5 for this to take effect.
The AN TX state machine uses these bits if the AN base pages ctrl
User base page high
bit is set. The following bits are defined:
•
•
The AN TX state machine generates the PRBS bit 49.
The AN TX state machine uses these bits if the AN next pages ctrl
User Next page low
bit is set. The following bits are defined:
•
•
•
•
•
For more information, refer to Clause 73.7.7.1 Next Page
encodings of IEEE 802.3ap-2007. Bit 49, the PRBS bit, is
generated by the AN TX state machine.
The AN TX state machine uses these bits if the AN next pages ctrl
User Next page high
bit is set. Bits [31:0] correspond to page bits [47:16]. Bit 49, the
PRBS bit, is generated by the AN TX state machine.
The AN RX state machine receives these bits from the link
LP base page low
partner. The following bits are defined:
•
•
•
•
•
•
The AN RX state machine received these bits from the link
LP base page high
partner. The following bits are defined:
•
•
•
The AN RX state machine receives these bits from the link
LP Next page low
partner. The following bits are defined:
•
•
•
•
•
For more information, refer to Clause 73.7.7.1 Next Page
encodings of IEEE 802.3ap-2007.
The AN RX state machine receives these bits from the link
LP Next page high
partner. Bits [31:0] correspond to page bits [47:16].
Received technology ability field bits of Clause 73 Auto-
AN LP ADV
Negotiation. The 10GBASE-KR PHY supports A0 and A2. The
Tech_A[24:0]
following protocols are defined:
Description
Bit-28 = = Pause Ability
AN_PAUSE [0]
Bit-29 = = Asymmetric Direction
AN_PAUSE [1]
Bit-30 = = Reserved
AN_PAUSE [2]
[29:5]: Correspond to page bits 45:21, the technology ability.
[4:0]: Correspond to bits 20:16, the TX nonce bits.
[15]: Next page bit
[14]: ACK, controlled by the state machine
[13]: Message Page (MP) bit
[12]: ACK2 bit
[11]: Toggle bit
[15] Next page bit
[14] ACK, which is controlled by the state machine
[13] RF bit
[12:10] Pause bits
[9:5] Echoed nonce which are set by the state machine
[4:0] Selector
[31:30]: Reserved
[29:5]: Correspond to page bits [45:21], the technology
ability
[4:0]: Correspond to bits [20:16], the TX Nonce bits
[15]: Next page bit
[14]: ACK which is controlled by the state machine
[13]: MP bit
[12] ACK2 bit
[11] Toggle bit
®
Intel Arria
continued...
®
10 Transceiver PHY User Guide
185