Intel Arria 10 User Manual page 252

Parameter
Number of word alignment patterns to
achieve sync
Number of invalid data words to lose
sync
Number of valid data words to
decrement error count
Enable
rx_std_wa_patternalign
Enable
rx_std_wa_a1a2size
Enable
rx_std_bitslipboundarysel
port
Enable port
rx_bitslip
Bit Reversal and Polarity Inversion
Enable TX bit reversal
Enable TX byte reversal
Enable TX polarity inversion
Enable port
tx_polinv
Enable RX bit reversal
Enable
rx_std_bitrev_ena
Enable RX byte reversal
Enable
rx_std_byterev_ena
Enable RX polarity inversion
Enable port
rx_polinv
Enable
rx_std_signaldetect
PCIe Ports
Enable PCIe dynamic datarate switch
ports
Enable PCIe
pipe_hclk_in
ports
pipe_hclk_out
Enable PCIe Gen3 analog control ports
Enable PCIe electrical idle control and
status ports
Enable PCIe
pipe_rx_polarity
Dynamic reconfiguration
Enable dynamic reconfiguration
Note: The signals in the left-most column are automatically mapped to a subset of a 128-bit
tx_parallel_data
Related Information
• How to Place Channels for PIPE Configurations
• Using the Arria 10 Transceiver Native PHY IP Core
® ®
Intel Arria 10 Transceiver PHY User Guide
252
Gen1 PIPE
3
16
15
Optional
port
port Off
Optional
Off
Off
Off
Off
Off
Off
port Off
Off
port Off
Off
Off
port Optional
Off
and
Enabled
Off
Enabled
port Enabled
Disabled
word when the Simplified Interface is enabled.
2. Implementing Protocols in Arria 10 Transceivers
Gen2 PIPE
3
16
15
Optional
Off
Optional
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Optional
Enabled
Enabled
Off
Enabled
Enabled
Disabled
on page 268
on page 45
UG-01143 | 2018.06.15
Gen3 PIPE
3
16
15
Optional
Off
Optional
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Optional
Enabled
Enabled
Enabled
Enabled
Enabled
Disabled