Intel Arria 10 User Manual page 410

Figure 198. Mix and Match Design Example
PLL Instances
In this example, two ATX PLL instances and five fPLL instances are used. Choose an
appropriate reference clock for each PLL instance. The IP Catalog lists the available
PLLs.
® ®
Intel Arria 10 Transceiver PHY User Guide
410
Transceiver Bank
ATX PLL
MCGB
6.25 GHz
Transceiver Bank
fPLL
5.15625 GHz
Transceiver Bank
x1
fPLL, 5.15625 GHz
fPLL, 625 MHz x1
Transceiver Bank
fPLL
mcgb_aux_clk0
2.5 GHz
ATX PLL
MCGB
4 GHz
Transceiver Bank
Legend
Interlaken12.5G
10GBASE-KR
1.25G/9.8G/10.3125G
3. PLLs and Clock Networks
Interlaken 12.5G
Interlaken 12.5G
x6
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
xN
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
x1
10GBASE-KR
10GBASE-KR
10GBASE-KR
10GBASE-KR
1.25G
1.25G
1.25G
1.25G
1.25G GbE
1.25G GbE
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
x6
xN
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
Unused
Unused
1.25G GbE
PCIe Gen 1/2/3
Unused channel
UG-01143 | 2018.06.15