Intel Arria 10 User Manual page 148

Signal Name
tx_latency_adj_10
g[15:0]
rx_latency_adj_1
g[21:0]
tx_latency_adj_1
g[21:0]
2.6.3.5.6. Dynamic Reconfiguration Interface
You can use the dynamic reconfiguration interface signals to dynamically change
between 1G and 10G data rates.
Table 120. Dynamic Reconfiguration Interface Signals
Signal Name
Output
rc_busy
Input
start_pcs_reconf
ig
Input
mode_1g_10gbar
2.6.3.6. Avalon-MM Register Interface
The Avalon-MM slave interface signals provide access to all registers.
Table 121. Avalon-MM Interface Signals
Signal Name Direction
Input
mgmt_clk
Input
mgmt_clk_res
et
Input
mgmt_addr[10
:0]
® ®
Intel Arria 10 Transceiver PHY User Guide
148
Direction Clock Domain
Output Synchronous to
xgmii_tx_clk
Output Synchronous to
gmii_rx_clk
Output Synchronous to
gmii_tx_clk
Direction Clock Domain
Synchronous to
mgmt_clk
Synchronous to
mgmt_clk
Synchronous to
mgmt_clk
Clock Domain
Clock
Asynchronous reset
Synchronous to
mgmt_clk
2. Implementing Protocols in Arria 10 Transceivers
When you enable 1588, this signal outputs the real time
latency in XGMII clock cycles (156.25 MHz) for the TX
PCS and PMA datapath for 10G mode. Bits 0 to 9
represent the fractional number of clock cycles. Bits 10 to
15 represent the number of clock cycles.
When you enable 1588, this signal outputs the real time
latency in GMII clock cycles (125 MHz) for the RX PCS and
PMA datapath for 1G mode. Bits 0 to 9 represent the
fractional number of clock cycles. Bits 10 to 21 represent
the number of clock cycles.
When you enable 1588, this signal outputs the real time
latency in GMII clock cycles (125 MHz) for the TX PCS and
PMA datapath for 1G mode. Bits 0 to 9 represent the
fractional number of clock cycles. Bits 10 to 21 represent
the number of clock cycles.
When asserted, indicates that reconfiguration is in
progress. Synchronous to the
only exposed under the following condition:
• Turn on Enable internal PCS reconfiguration logic
When asserted, initiates reconfiguration of the PCS.
Sampled with the
mgmt_clk
under the following condition:
• Turn on Enable internal PCS reconfiguration logic
This signal selects either the 1G or 10G tx-parallel-data
going to the PCS. It is only used for the 1G/10G
application (variant) under the following circumstances:
• the Sequencer (auto-rate detect) is not enabled
• 1G mode is enabled
Description
The clock signal that controls the Avalon-MM PHY management
interface. If you plan to use the same clock for the PHY
management interface and transceiver reconfiguration, you must
restrict the frequency to 100-125 MHz to meet the specification
for the transceiver reconfiguration clock.
Resets the PHY management interface. This signal is active high
and level sensitive.
11-bit Avalon-MM address.
UG-01143 | 2018.06.15
Description
Description
. This signal is
mgmt_clk
. This signal is only exposed
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