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2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Table 129.
Clock and Reset Signals
Signal Name
tx_serial_clk_10g
tx_serial_clk_1g
rx_cdr_ref_clk_10g
rx_cdr_refclk_1g
mgmt_clk
mgmt_clk_reset
xgmii_tx_clk
xgmii_rx_clk
tx_clkout
rx_clkout
tx_pma_clkout
rx_pma_clkout
tx_div_clk
rx_div_clk
Direction
Input
High speed clock from the 10G PLL to drive 10G PHY TX PMA. The
frequency of this clock is 5.15625 GHz.
Input
The clock from the external 1G PLL to drive the TX high speed serial
interface (HSSI) circuits. Connected to the
the native PHY.
Input
10G PHY RX PLL reference clock. This clock frequency can be
644.53125 MHz or 322.2656 MHz.
Input
The RX 1G PLL reference clock to drive the RX HSSI circuits.
Connected to the
Input
Avalon-MM clock and control system clock. Its frequency range is
100 MHz to 125 MHz.
Input
When asserted, it resets the whole PHY.
Input
Clock for XGMII TX interface with MAC. Can be connected to
tx_div_clkout
PHY.
Input
The clock for the XGMII RX interface with the MAC. Intel
recommends connecting it directly to a PLL for use with TSE. This
drives
rx_coreclkin
312.5 MHz.
Output
Transmit parallel clock. It is sourced from
out_pld_pcs_tx_clk_out
provide the XGMII clocks or the GMII clocks, though if the PHY is
reconfigured, the frequency changes. Its frequency is 125, 156.25,
161, 258, or 312.5 MHz.
Output
Receive parallel clock. It is sourced from
out_pld_pcs_rx_clk_out
the frequency changes. Its frequency is 125, 156.25, 161, 258, or
312.5 MHz.
Output
Transmit PMA clock. This is the clock for the 1588 mode TX FIFO and
the 1G TX and RX PCS parallel data interface. Note: Use
tx_div_clkout
This clock is provided for the 1G mode GMII/MII data and SyncE
mode where the clock can be used as a reference to lock an external
clock source. Its frequency is 125, 161, or 258 MHz.
Output
Receive PMA clock. This is the clock for the 1588 mode RX FIFO and
the 1G RX FIFO. Note: Use
10G RX datapath clocking. This clock is provided for the SyncE mode
where the clock can be used as a reference to lock an external clock
source. Its frequency is 125, 161, or 258 MHz.
Output
This is the transmit div33 clock, which is sourced from the Native
PHY
tx_pma_div_clkout
xgmii_tx_clk
interface, though if the PHY is reconfigured to 1G mode, the
frequency changes. Its frequency is 125, 156.25, or 312.5 MHz.
Output
This is the receive div33 clock, which is recovered from the received
data. It drives the Auto Negotiation (AN) and Link Training (LT) logic
and is sourced from the Native PHY
Note: Use
tx_clkout
clocking. If the PHY is reconfigured to 1G mode, the frequency
changes. Its frequency is 125, 156.25, or 312.5 MHz.
Description
tx_serial_clk
input of the native PHY.
rx_cdr_refclk
. This drives the
tx_coreclkin
of the native PHY. Its frequency is 156.25 or
on the HSSI. This could be used to
on the HSSI. If the PHY is reconfigured,
or
for 10G TX datapath clocking.
xgmii_tx_clk
or
tx_div_clkout
. It could be connected to the
and
clock inputs to drive the MAC
xgmii_rx_clk
rx_pma_div_clkout
or
for 10G TX datapath
xgmii_rx_clk
®
®
Intel
Arria
10 Transceiver PHY User Guide
input of
port of the Native
for
xgmii_rx_clk
port.
continued...
169
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