Intel Arria 10 User Manual page 90

Name
rx_syncstatus[<n><w>/
<s>-1:0]
Table 73. Word Aligner and Bitslip
Name
tx_std_bitslipboundary
sel[5 <n>-1:0]
rx_std_bitslipboundary
sel[5 <n>-1:0]
rx_std_wa_patternalig
n[<n>-1:0]
rx_std_wa_a1a2size[<n>
-1:0]
rx_bitslip[<n>-1:0]
Table 74. Bit Reversal and Polarity Inversion
Name
rx_std_byterev_ena[<n>
-1:0]
rx_std_bitrev_ena[<n>-
1:0]
® ®
Intel Arria 10 Transceiver PHY User Guide
90
Direction Clock Domain
Output Asynchronous
Direction Clock Domain
Input Asynchronous
Output Asynchronous
Input Synchronous
to
rx_clkout
Input Asynchronous
Input Asynchronous
Direction Clock Domain
Input Asynchronous
Input Asynchronous
2. Implementing Protocols in Arria 10 Transceivers
Description
. For each 128-bit word,
rx_parallel_data
corresponds to
rx_patterndetect
.
rx_parallel_data[12]
When asserted, indicates that the conditions required for
synchronization are being met.
. For each 128-bit word,
rx_parallel_data
corresponds to
rx_syncstatus
Description
Bitslip boundary selection signal. Specifies the number of
bits that the TX bit slipper must slip.
This port is used in deterministic latency word aligner mode.
This port reports the number of bits that the RX block
slipped. This port values should be taken into consideration
in either Deterministic Latency Mode or Manual Mode of
Word Aligner.
Active when you place the word aligner in manual mode. In
manual mode, you align words by asserting
rx_std_wa_patternalign
width is 10 bits,
rx_std_wa_patternalign
sensitive. For all the other PCS-PMA Interface widths,
rx_std_wa_patternalign
You can use this port only when the word aligner is
configured in manual or deterministic latency mode.
When the word aligner is in manual mode, and the PCS-PMA
interface width is 10 bits, this is a level sensitive signal. In
this case, the word aligner monitors the input data for the
word alignment pattern, and updates the word boundary
when it finds the alignment pattern.
For all other PCS-PMA interface widths, this signal is edge
sensitive.This signal is internally synchronized inside the
PCS using the PCS parallel clock and should be asserted for
at least 2 clock cycles to allow synchronization.
Used for the SONET protocol. Assert when the A1 and A2
framing bytes must be detected. A1 and A2 are SONET
backplane bytes and are only used when the PMA data
width is 8 bits.
Used when word aligner mode is bitslip mode. When the
Word Aligner is in either Manual (PLD controlled),
Synchronous State Machine or Deterministic Latency ,the
is not valid and should be tied to 0.
rx_bitslip signal
For every rising edge of the
rx_std_bitslip
word boundary is shifted by 1 bit. Each bitslip removes the
earliest received bit from the received data.
Description
This control signal is available when the PMA width is 16 or
20 bits. When asserted, enables byte reversal on the RX
interface. Used if the MSB and LSB of the transmitted data
are erroneously swapped.
When asserted, enables bit reversal on the RX interface. Bit
order may be reversed if external transmission circuitry
transmits the most significant bit first. When enabled, the
UG-01143 | 2018.06.15
is a part of
rx_syncstatus
rx_parallel_data[10]
. When the PCS-PMA Interface
is level
is positive edge sensitive.
signal, the
continued...
.