Intel Arria 10 User Manual page 244

Figure 105. Use ATX PLL or fPLL for Gen1/Gen2/Gen3 x4 Mode
fPLL1
ATX PLL1
Notes:
1. The figure shown is just one possible combination for the PCIe Gen1/Gen2/Gen3 x4 mode.
2. The x6 and xN clock networks are used for channel bonding applications.
3. Each master CGB drives one set of x6 clock lines.
4. Gen1/Gen2 modes use the fPLL only.
5. Gen3 mode uses the ATX PLL only.
6. Use the pll_pcie_clk from the fPLL, configured as Gen1/Gen2. This is the hclk required by the PIPE interface.
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Intel Arria 10 Transceiver PHY User Guide
244
XN
Network
6
Connections Done
via X1 Network
Master
CGB
Master
CGB
2. Implementing Protocols in Arria 10 Transceivers
X6
Network
6 6
6
6
6
UG-01143 | 2018.06.15
Ch 5
CGB
CDR
Ch 4
CGB
CDR
Ch 3
CGB
CDR
Ch 2
CGB
CDR
Ch 1
CGB
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Ch 0
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CDR