Intel Arria 10 User Manual page 173

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Parameter Name
Enable 10Mb/100Mb
Ethernet functionality
PHY ID (32 bits)
PHY core version (16 bits)
2.6.4.5.4. Speed Detection Parameters
Selecting the speed detection option gives the PHY the ability to detect to link partners
that support 1G/10GbE but have disabled Auto-Negotiation. During Auto-Negotiation,
if AN cannot detect Differential Manchester Encoding (DME) pages from a link partner,
the Sequencer reconfigures to 1GbE and 10GbE modes (Speed/Parallel detection) until
it detects a valid 1G or 10GbE pattern.
Table 134. Speed Detection
Parameter Name
Enable automatic speed
detection
Avalon-MM clock frequency
Link fail inhibit time for
10Gb Ethernet
Link fail inhibit time for
1Gb Ethernet
Enable PCS-Mode port
2.6.4.5.5. PHY Analog Parameters
You can specify analog parameters using the Intel Quartus Prime Assignment Editor,
the Pin Planner, or the Intel Quartus Prime Settings File (.qsf).
Options
Off
On When you turn this option on, the core includes the MII PCS. It
also supports 4-speed mode to implement a 10M/100M interface
Off
to the MAC for the GbE line rate.
32-bit value An optional 32-bit value that serves as a unique identifier for a
particular type of PCS. The identifier includes the following
components:
• Bits 3-24 of the Organizationally Unique Identifier (OUI)
assigned by the IEEE
• 6-bit model number
• 4-bit revision number
If unused, do not change the default value which is
0x00000000.
16-bit value This is an optional 16-bit value that identifies the PHY core
version.
Options
On When you turn this option On, the core includes the Sequencer
block that sends reconfiguration requests to detect 1G or 10GbE
Off
when the Auto Negotiation block is not able to detect AN data.
Specifies the clock frequency for
100-162 MHz
Specifies the time before
504 ms
link fails if the
link_status
more information, refer to "Clause 73 Auto Negotiation for
Backplane Ethernet" in IEEE Std 802.3ap-2007.
Specifies the time before
40-50 ms
link fails if the
link_status
On Enables or disables the PCS-Mode port.
Off
Description
Description
phy_mgmt_clk
is set to FAIL or OK. A
link_status
link_fail_inhibit_time
is set to OK. The legal range is 500-510 ms. For
is set to FAIL or OK . A
link_status
link_fail_inhibit_time
is set to OK. The legal range is 40-50 ms.
® ®
Intel Arria 10 Transceiver PHY User Guide
.
has expired before
has expired before
173