Intel Arria 10 User Manual page 305

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
The RX bit slip feature is optional and may or may not be enabled.
Figure 137. RX Bit Slip in 8-bit Mode
tx_parallel_data
rx_std_bitslipboundarysel
tx_parallel_data
rx_parallel_data
Figure 138. RX Bit Slip in 10-bit Mode
tx_parallel_data
rx_std_bitslipboundarysel
Figure 139. RX Bit Slip in 16-bit Mode
tx_parallel_data
rx_std_bitslipboundarysel
Figure 140. RX Bit Slip in 20-bit Mode
tx_parallel_data
rx_std_bitslipboundarysel
2.9.2.4. RX Polarity Inversion
Receiver polarity inversion can be enabled in low latency, basic, and basic rate match
modes.
To enable the RX polarity inversion feature, select the Enable RX polarity inversion
and Enable rx_polinv port options.
This mode adds
rx_polinv
rx_polinv
You can verify this feature by monitoring
= 8'hbc
01111
rx_bitslip
bc
00 97
= 10'h3bc
01111
rx_bitslip
tx_parallel_data 3bc
rx_parallel_data 000 1de
= 16'hfcbc
00001 00010
rx_bitslip
tx_parallel_data fcbc
rx_parallel_data 979f cbcf
= 20'h3fcbc
00001 00010
rx_bitslip
tx_parallel_data 3fcbc
rx_parallel_data e5e1f f2f0f
. If there is more than one channel in the design,
rx_polinv
is a bus in which each bit corresponds to a channel. As long as
is asserted, the RX data received has a reverse polarity.
cb e5 f2
0ef 277 33b 39d 3ce
00011 00100
e5e7 f2f3
00011 00100 00101
f9787 fcbc3 de5e1
rx_parallel_data
®
Intel
79 bc
1e7 2f3 379 3bc
00101 00110
f979 fcbc
00110 00111 01000
ff2f0 7f978 3fcbc
.
®
Arria 10 Transceiver PHY User Guide
305