Intel Arria 10 User Manual page 306

Transceiver phy
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Figure 141. RX Polarity Inversion
rx_polinv
tx_parallel_data
rx_parallel_data
rx_patterndetect
rx_syncstatus
2.9.2.5. RX Bit Reversal
The RX bit reversal feature can be enabled in low latency, basic, and basic rate match
mode. The word aligner is available in any mode, bit slip, manual, or synchronous
state machine.
To enable this feature, select the Enable RX bit reversal and Enable
rx_std_bitrev_ena port options. This adds
than one channel in the design,
bit corresponds to a channel. As long as
data received by the core shows bit reversal.
You can verify this feature by monitoring
Figure 142. RX Bit Reversal
rx_std_bitrev_ena
tx_parallel_data
rx_parallel_data
rx_patterndetect
rx_syncstatus
2.9.2.6. RX Byte Reversal
The RX byte reversal feature can be enabled in low latency, basic, and basic rate
match mode. The word aligner is available in any mode.
To enable this feature, select the Enable RX byte reversal and Enable
rx_std_byterev_ena port options. This adds
more than one channel in the design,
each bit corresponds to a channel. As long as
RX data received by the core shows byte reversal.
You can verify this feature by monitoring
Figure 143. RX Byte Reversal
rx_std_byterev_ena
tx_parallel_data
rx_parallel_data
rx_patterndetect
rx_syncstatus
2.9.2.7. Rate Match FIFO in Basic (Single Width) Mode
Only the rate match FIFO operation is covered in these steps.
®
®
Intel
Arria
10 Transceiver PHY User Guide
306
11111100001110111100
11111100001...
00000011110001000011
01
11
rx_std_bitrev_ena
11111100001110111100
11111100001110111100
00111101110000111111
01
00
11
11111100001110111100
111111...
11101111001111110000
01
10
11
2. Implementing Protocols in Arria 10 Transceivers
rx_std_bitrev_ena
becomes a bus in which each
rx_std_bitrev_ena
rx_parallel_data
rx_std_byterev_ena
rx_std_byterev_ena
rx_std_byterev_ena
rx_parallel_data
UG-01143 | 2018.06.15
11111100001110111100
. If there is more
is asserted, the RX
.
11111100001110111100
01
. If there is
becomes a bus in which
is asserted, the
.
11111100001110111100
01

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