Intel Arria 10 User Manual page 223

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Figure 87. XAUI Top-Level Signals—Soft PCS and PMA
SDR TX XGMII
SDR RX XGMII
Avalon-MM PHY
Management
Interface
2.6.6.9. XAUI PHY Interfaces
The XAUI PCS interface to the FPGA fabric uses a SDR XGMII interface. This interface
implements a simple version of the Avalon-ST protocol. The interface does not include
ready or valid signals. Consequently, the sources always drive data and the sinks must
always be ready to receive data.
For more information about the Avalon-ST protocol, including timing diagrams, refer to
the Avalon Interface Specifications.
Depending on the parameters you choose, the application interface runs at either
156.25 Mbps or 312.5 Mbps. At either frequency, data is only driven on the rising edge
of clock. To meet the bandwidth requirements, the datapath is eight bytes wide with
eight control bits, instead of the standard four bytes of data and four bits of control.
The XAUI PHY IP core treats the datapath as two, 32-bit data buses and includes logic
to interleave them, starting with the low-order bytes.
Figure 88. Interleaved SDR XGMII Data Mapping
Original XGMII Data
[63:56]
[63:56]
Related Information
Avalon Interface Specifications
xgmii_tx_dc[71:0]
xgmii_tx_clk
xgmii_rx_dc[71:0]
xgmii_rx_clk
xgmii_rx_inclk
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_address[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
pll_ref_clk
Clocks
cdr_ref_clk
pll_locked_i
pll_powerdown_o
PLL
tx_bonding_clock[5:0]
pll_cal_busy_i
[55:48] [47:40]
[31:24] [55:48]
XAUI Top-Level Signals
xaui_rx_serial_data[3:0]
xaui_tx_serial_data[3:0]
rx_channelaligned
rx_disperr[7:0]
rx_errdetect[7:0]
rx_syncstatus[7:0]
reconfig_clk
reconfig_reset
reconfig_address[11:0]
reconfig_writedata[31:0]
reconfig_readdata[31:0]
reconfig_write
reconfig_read
reconfig_waitrequest
rx_recovered_clk[3:0]
[39:32] [31:24] [23:16]
Interleaved Result
[23:16] [47:40] [15:8]
®
Intel Arria
Transceiver
Serial Data
RX Status
Optional
Avalon-MM
Dynamic
Reconfiguration
PMA
Channel
rx_ready
tx_ready Controller
[15:8] [7:0]
[39:32] [7:0]
®
10 Transceiver PHY User Guide
223