Intel Arria 10 User Manual page 296

Enable rx_enh_fifo_del port (10GBASE-R)
Enable rx_enh_fifo_insert port (10GBASE-R)
Enable rx_enh_fifo_rd_en port (Interlaken)
Enable rx_enh_fifo_align_val port (Interlaken)
Enable rx_enh_fifo_align_cir port (Interlaken)
Enable TX 64b/66b encoder
Enable RX 64b/66b decoder
Enable TX sync header error insertion
Enable RX block synchronizer
Enable rx_enh_blk_lock port
Enable TX data bitslip
Enable TX data polarity inversion
Enable RX data bitslip
Enable RX data polarity inversion
Enable tx_enh_bitslip port
Enable rx_bitslip port
Enable RX KR-FEC error marking
Error marking type
Enable KR-FEC TX error insertion
KR-FEC TX error insertion spacing
Enable tx_enh_frame port
Enable rx_enh_frame port
Enable rx_enh_frame_dian_status port
Table 215. Dynamic Reconfiguration Parameters
Enable dynamic reconfiguration
Share reconfiguration interface
Enable Altera Debug Master Endpoint
Enable embedded debug
Enable capability registers
Set user-defined IP identifier
Enable control and status registers
Enable prbs soft accumulators
Configuration file prefix
Generate SystemVerilog package file
Generate C header file
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Intel Arria 10 Transceiver PHY User Guide
296
Parameter
Parameter
2. Implementing Protocols in Arria 10 Transceivers
Range
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
10G, 40G
On / Off
On / Off
On / Off
On / Off
On / Off
Range
On / Off
On / Off
On / Off
On / Off
On / Off
number
On / Off
On / Off
text string
On / Off
On / Off
UG-01143 | 2018.06.15