Intel Arria 10 User Manual page 251

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Parameter
FPGA Fabric / Standard TX PCS interface
width
FPGA Fabric / Standard RX PCS interface
width
Enable Standard PCS low latency mode
Standard PCS FIFO
TX FIFO mode
RX FIFO mode
Enable
tx_std_pcfifo_full
Enable
tx_std_pcfifo_empty
Enable
rx_std_pcfifo_full
Enable
rx_std_pcfifo_empty
Byte Serializer and Deserializer
TX byte serializer mode
RX byte deserializer mode
8B/10B Encoder and Decoder
Enable TX 8B/10B encoder
Enable TX 8B/10B disparity control
Enable RX 8B/10B decoder
Rate Match FIFO
Rate Match FIFO mode
RX rate match insert / delete -ve pattern
(hex)
RX rate match insert / delete +ve
pattern (hex)
Enable
rx_std_rmfifo_full
Enable
rx_std_rmfifo_empty
PCI Express Gen 3 rate match FIFO
mode
Word Aligner and Bit Slip
Enable TX bit slip
Enable
tx_std_bitslipboundarysel
port
RX word aligner mode
RX word aligner pattern length
RX word aligner pattern (hex)
Gen1 PIPE
8, 16
8, 16
Off
low_latency
low_latency
port Optional
port Optional
Optional
port
port Optional
Disabled, Serialize x2
Disabled, Serialize x2
Enabled
Enabled
Enabled
PIPE, PIPE 0ppm
0x0002f17c (K28.5/
K28.0/)
0x000d0e83 (K28.5/
K28.0/)
Optional
port
port Optional
Bypass
Off
Optional
Synchronous State
Machine
10
0x0000 00000000017c (/
K28.5/)
Gen2 PIPE
16
16
Off
low_latency
low_latency
Optional
Optional
Optional
Optional
Serialize x2
Serialize x2
Enabled
Enabled
Enabled
PIPE, PIPE 0ppm
0x0002f17c (K28.5/ 0x0002f17c (K28.5/
K28.0/)
0x000d0e83 (K28.5/
K28.0/)
Optional
Optional
Bypass
Off
Optional
Synchronous State
Machine
10
0x0000 00000000017c (/
K28.5/)
® ®
Intel Arria 10 Transceiver PHY User Guide
Gen3 PIPE
32
32
Off
low_latency
low_latency
Optional
Optional
Optional
Optional
Serialize x4
Deserialize x4
Enabled
Enabled
Enabled
PIPE, PIPE 0ppm
K28.0/)
0x000d0e83
(K28.5/K28.0/)
Optional
Optional
600
Off
Optional
Synchronous State
Machine
10
0x0000
00000000017c(/
K28.5/)
continued...
251