Intel Arria 10 User Manual page 139

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Refer to
2. Select Backplane-KR from the IP variant list located under Ethernet Intel
FPGA IP Core Type.
3. Use the parameter values in the tables in
10GBASE-KR Auto-Negotiation and Link Training Parameters
10GBASE-KR Optional Parameters
modify the setting to meet your specific requirements.
4. Click Generate HDL to generate the 10GBASE-KR PHY IP core top-level HDL
file.
Note: You might observe timing violations. If the timing path is within the IP, you can ignore
these violations. This will be fixed in a future release of the Intel Quartus Prime
software.
Related Information
• Using the Arria 10 Transceiver Native PHY IP Core
• 10GBASE-KR Auto-Negotiation and Link Training Parameters
2.6.3.4.1. General Options
The General Options allow you to specify options common to 10GBASE-KR mode.
Table 108. General Options Parameters
Parameter Name
Enable internal PCS
reconfiguration logic
Enable IEEE 1588 Precision
Time Protocol
Enable M20K block ECC
protection
Enable tx_pma_clkout port
Enable rx_pma_clkout port
Enable tx_divclk port
Enable rx_divclk port
Enable tx_clkout port
Select and Instantiate the PHY IP Core
Options
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
on page 33.
10GBASE-R Parameters
on page 141 as a starting point. You can then
on page 45
Description
This parameter is only an option when
set to 0, it does not include the reconfiguration module or
expose the
start_pcs_reconfig
to 1, it provides a simple interface to initiate reconfiguration
between 1G and 10G modes.
When you turn on this parameter, you enable the IEEE 1588
Precision Time Protocol logic for both 1G and 10G modes.
When you turn on this parameter, you enable error correction
code (ECC) support on the embedded Nios CPU system. This
parameter is only valid for the backplane variant.
When you turn on this parameter, the
enabled. Refer to the Clock and Reset Interfaces section for
more information about this port.
When you turn on this parameter, the
enabled. Refer to the Clock and Reset Interfaces section for
more information about this port.
When you turn on this parameter, the
enabled. Refer to the Clock and Reset Interfaces section for
more information about this port.
When you turn on this parameter, the
enabled. Refer to the Clock and Reset Interfaces section for
more information about this port.
When you turn on this parameter, the
enabled. Refer to the Clock and Reset Interfaces section for
more information about this port.
®
Intel Arria
on page 140,
on page 140, and
on page 140
= 0. When
SYNTH_SEQ
or ports. When set
rc_busy
port is
tx_pma_clkout
port is
rx_pma_clkout
port is
tx_divclk
port is
rx_divclk
port is
tx_clkout
continued...
®
10 Transceiver PHY User Guide
139