Intel Arria 10 User Manual page 366

Port
pll_refclk2
pll_refclk3
pll_refclk4
tx_serial_clk
pll_locked
hssi_pll_cascade_clk
pll_pcie_clk
reconfig_clk0
reconfig_reset0
reconfig_write0
reconfig_read0
reconfig_address0[9:0]
reconfig_writedata0[31:0]
reconfig_readdata0[31:0]
reconfig_waitrequest0
pll_cal_busy
mcgb_rst
mcgb_aux_clk0
tx_bonding_clocks[5:0]
mcgb_serial_clk
pcie_sw[1:0]
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Intel Arria 10 Transceiver PHY User Guide
366
Direction Clock Domain
input N/A
input N/A
input N/A
output N/A
output Asynchronous
output N/A
output N/A
input N/A
input reconfig_clk0
input reconfig_clk0
input reconfig_clk0
input reconfig_clk0
input reconfig_clk0
output reconfig_clk0
output reconfig_clk0
output Asynchronous
input Asynchronous
input N/A
output N/A
output N/A
input Asynchronous
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Description
Reference clock input port 2.
Reference clock input port 3.
Reference clock input port 4.
High speed serial clock output port
for GX channels. Represents the x1
clock network.
Active high status signal which
indicates if PLL is locked.
fPLL cascade clock output port
Used for PCIe.
Optional Avalon interface clock. Used
for PLL reconfiguration.
Used to reset the Avalon interface.
Asynchronous to assertion and
synchronous to deassertion.
Active high write enable signal.
Active high read enable signal.
10-bit address bus used to specify
address to be accessed for both read
and write operations.
32-bit data bus. Carries the write
data to the specified address.
32-bit data bus. Carries the read
data from the specified address.
Indicates when the Avalon interface
signal is busy. When asserted, all
inputs must be held constant.
Status signal which is asserted high
when PLL calibration is in progress.
Perform logical OR with this signal
and the port on the
tx_cal_busy
reset controller IP.
Master CGB reset control.
Deassert this reset at the same time
as .
pll_powerdown
Used for PCIe to switch between
fPLL/ATX PLL during link speed
negotiation.
Optional 6-bit bus which carries the
low speed parallel clock outputs from
the Master CGB.
Used for channel bonding, and
represents the x6/xN clock network.
High speed serial clock output for
x6/xN non-bonded configurations.
2-bit rate switch control input used
for PCIe protocol implementation.
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