Intel Arria 10 User Manual page 140

Parameter Name
Enable rx_clkout port
Enable Hard PRBS support
and ADME support
Reference clock frequency
Enable additional control
and status ports
Include FEC sublayer
Set bit on
FEC_ability
power up and reset
Set bit on
FEC_Enable
power up and reset
Related Information
Clock and Reset Interfaces
2.6.3.4.2. 10GBASE-R Parameters
The 10GBASE-R parameters specify basic features of the 10GBASE-R PCS. The FEC
options also allow you to specify the FEC ability.
Table 109. 10GBASE-R Parameters
Parameter Name
10GbE Reference clock
frequency
Enable additional control
and status ports
Table 110. FEC Options
Parameter Name
Include FEC sublayer
2.6.3.4.3. 10GBASE-KR Auto-Negotiation and Link Training Parameters
Table 111. Auto Negotiation and Link Training Settings
Name
Enable Auto-Negotiation
® ®
Intel Arria 10 Transceiver PHY User Guide
140
Options
On
When you turn on this parameter, the
enabled. Refer to the Clock and Reset Interfaces section for
Off
more information about this port.
On When you turn on this parameter, you enable the ADME and
Hard PRBS data generation and checking logic in the Native PHY.
Off
The transceiver toolkit (TTK) requires ADME to be enabled in the
Native PHY IP core.
644.53125 MHz Specifies the input reference clock frequency. The default is
322.265625 MHz.
322.265625 MHz
On
When you turn this option on, the core includes the
Off
rx_block_lock
On When you turn on this parameter, the core includes logic to
implement FEC and a soft 10GBASE-R PCS. This is applicable
Off
only for the 10G mode.
On
When you turn on this parameter, the core sets the
Off
FEC Ability
and reset, causing the core to assert the FEC ability. This option
is required for FEC functionality.
On
When you turn on this parameter, the core sets the
Off
Request
the core to request the FEC ability during Auto Negotiation. This
option is required for FEC functionality.
on page 143
Options
644.53125 MHz Specifies the input reference clock frequency. The default is
322.265625 MHz.
322.265625 MHz
On
When you turn on this parameter, the core includes the
Off
rx_block_lock
Options
On When you turn on this parameter, the core includes logic to
implement FEC and a soft 10GBASE-R PCS.
Off
Range
On Enables or disables the Auto-Negotiation feature.
2. Implementing Protocols in Arria 10 Transceivers
Description
rx_clkout
and output.
rx_hi_ber
bit (0xB0[16]) FEC ability bit during power up
bit ( ) during power up and reset, causing
0xB0[18]
Description
and ports.
rx_hi_ber
Description
Description
UG-01143 | 2018.06.15
port is
Assert KR
KR FEC
continued...