Intel Arria 10 User Manual page 183

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Word Bit R/W
Addr
16 R
17 R
0x4B2 0:10 RW
11 RWSC
31:15 RWSC
0x4B5
to
0x4BF
0x4C0 0 RW
(36)
1 RW
2 RW
3 RW
4 RW
5 RW
0x4C1 0 RW
4 RW
8 RW
0x4C2 1 RO
(36)
These register bits are only applicable to the 10GBASE-KR mode.
Name
When set to 1, indicates that the 10GBASE-KR PHY supports FEC.
KR FEC ability
Set as parameter
170.0
Clause 45.2.1.84 of IEEE 802.3ap-2007.
When set to 1, indicates that the 10GBASE-KR PHY is capable of
KR FEC err ind
reporting FEC decoding errors to the PCS. For more information,
ability 170.0
refer to Clause 74.8.3 of IEEE 802.3ap-2007.
Reserved —
Writing a 1 inserts one error pulse into the TX FEC depending on
KR FEC TX Error
the transcoder and burst error settings.
Insert
Reserved —
Reserved for 40G KR Intentionally left empty for address compatibility with 40G MAC +
PHY KR solutions.
When set to 1, enables the AN function. The default value is 1.
AN enable
For additional information, refer to bit 7.0.12 in Clause 73.8
Management Register Requirements of IEEE 802.3ap-2007.
When set to 1, the user base pages are enabled. You can send
AN base pages ctrl
any arbitrary data via the user base page low/high bits. When set
to 0, the user base pages are disabled and the state machine
generates the base pages to send.
When set to 1, the user next pages are enabled. You can send
AN next pages ctrl
any arbitrary data via the user next page low/high bits. When set
to 0, the user next pages are disabled. The state machine
generates the null message to send as next pages.
When set to 1, the local device signals Remote Faults in the AN
Local device remote
pages. When set to 0, a fault has not occurred.
fault
When set to 1, forces the TX nonce value to support some UNH
Force TX nonce
testing modes. When set to 0, this is normal operation.
value
When set to 1, overrides the
Override AN
parameters and uses the bits in 0x4C3 instead. You must reset
Parameters Enable
the Sequencer to reconfigure and restart into AN mode. When set
to 0, this is normal operation and is used with 0x4B0 bit 0 and
0x4C3 bits[30:16].
When set to 1, resets all the 10GBASE-KR AN state machines.
Reset AN
This bit is self clearing.
When set to 1, restarts the 10GBASE-KR TX state machine. This
Restart AN TX SM
bit self clears and is active only when the TX state machine is in
the AN state. For more information, refer to bit 7.0.9 in Clause
73.8 Management Register Requirements of IEEE 802.3ap-2007.
When asserted, new next page (NP) info is ready to send. The
AN Next Page
data is in the XNP TX registers. When 0, the TX interface sends
null pages. This bit self clears. NP is encoded in bit D15 of Link
Codeword. For more information, refer to Clause 73.6.9 and bit
7.16.15 of Clause 45.2.7.6 of IEEE 802.3ap-2007.
When set to 1, a page has been received. When 0, a page has not
AN page received
been received. The current value clears when the register is read.
For more information, refer to bit 7.1.6 in Clause 73.8 of IEEE
802.3ap-2007.
Description
. For more information, refer to
SYNTH_FEC
,
AN_TECH AN_FEC
® ®
Intel Arria 10 Transceiver PHY User Guide
, and
AN_PAUSE
continued...
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