Intel Arria 10 User Manual page 198

Figure 78. 1G/10GbE PHY Only Design Example
A10_DE_WRAPPER
ISSP
Related Information
Arria 10 Transceiver PHY Design Examples
2.6.4.12. Simulation Support
The 1G/10GbE and 10GBASE-KR PHY IP core supports the following Intel-supported
simulators for this Quartus Prime software release:
• ModelSim Verilog
• ModelSim VHDL
• VCS Verilog
• VCS VHDL
• NCSIM Verilog
• NCSIM VHDL simulation
When you generate a 1G/10GbE or 10GBASE-KR PHY IP core, the Quartus Prime
software optionally generates an IP functional simulation model.
® ®
Intel Arria 10 Transceiver PHY User Guide
198
Management
Master
JTAG-to-
Avalon-MM
Master
A10_IP_WRAPPER
Clock and
Reset
1G/10GbE PHY IP
XGMII
CLK FPLL
1G Ref CLK
1588 Soft
CMU PLL
FIFOs
10G Ref CLK
Sequencer
ATX PLL
Reset
Control
Reset
Control
Reset
Control
Reset
Control
CH0: PHY_ADDR = 0x0 nnn
CH1: PHY_ADDR = 0x1 nnn
CH2: PHY_ADDR = 0x2 nnn
CH3: PHY_ADDR = 0x3 nnn
2. Implementing Protocols in Arria 10 Transceivers
Test Harness
XGMII XGMII XGMII
Test Harness
Source Sink GEN
XGMII XGMII
Source Sink
A10
Reconfiguration
KR PHY IP
NF
KR PHY IP
Reconfiguration
KR PHY IP
STD
1588 Soft
TX PCS
FIFOs
1588 Soft
STD
FIFOs 1588 Soft
TX PCS
FIFOs
TX PCS
Sequencer
10-GB
GMII
Sequencer
TX PCS
RS
Sequencer
10-GB
GMII
TX PCS
10-GB
RS
GMII
TX PCS
RS GMII
STD
RS
Auto Neg
RX PCS
cls 73
STD
Auto Neg
RX PCS
cls 73
Auto Neg
cls 73
Link Training RX PCS
cls 72 10-GB
Link Training
RX PCS
cls 72
Link Training
10-GB
cls 72
RX PCS
10-GB
RX PCS
Divide
UG-01143 | 2018.06.15
TH0_ADDR = 0xF nnn
XGMII
TH1_ADDR = 0xE nnn
...
CHK
XGMII XGMII
...
GEN CHK
Registers CSR
Avalon-MM Slave
Registers CSR
Avalon-MM Slave
NF Registers CSR
Native Hard PHY
Reconfiguration Avalon-MM Slave
NF Registers CSR
Reconfiguration Native Hard PHY Avalon-MM Slave
TX PMA
Native Hard PHY
Native Hard PHY
TX PMA
STD
TX PMA
STD
TX PMA
TX PCS
10-GB
TX PCS
STD
STD
RX PCS
RX PMA
RX PMA
RX PMA
10-GB
RX PMA
RX PCS
Divide
Divide
Divide