Intel Arria 10 User Manual page 380

Figure 177. xN Clock Network
The maximum channel span of a xN clock network is two transceiver banks above and
two transceiver banks below the bank that contains the driving PLL and the master
CGB. A maximum of 30 channels can be used in a single bonded or non-bonded xN
group.
The maximum data rate supported by the xN clock network while driving channels in
either the bonded or non-bonded mode depends on the voltage used to drive the
transceiver banks.
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Intel Arria 10 Transceiver PHY User Guide
380
xN Up xN Down
Top
Master
CGB1
Master
CGB0
xN Up xN Down
3. PLLs and Clock Networks
x6 x6
Bottom
CGB
CGB
CMU or CDR
CGB
CGB
CGB
CMU or CDR
CGB
UG-01143 | 2018.06.15
Ch 5
CDR
Ch 4
Ch 3
CDR
Ch 2
CDR
Ch 1
Ch 0
CDR