Intel Arria 10 User Manual page 137

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Figure 68. 10GBASE-KR PHY IP Core Block Diagram
10GBASE-KR PHY IP
Avalon-MM
Nios II Sequencer
Interface
XGMII_TX_CLK
TX_GMII_DATA
TX_XGMII_DATA
Nios II LT Interface
TX_PMA_CLKOUT
RX_XGMII_DATA
XGMII_RX_CLK
RX_GMII_DATA
Soft Logic
Note: The 10GBASE-KR PHY IP core does not support backplane applications with IEEE 1588
Precision Time Protocol.
The 10GBASE-KR PHY IP core includes the following components:
Standard and Enhanced PCS Datapaths
The Enhanced PCS and PMA inside the Native PHY are configured to be the 10GBASE-
R PHY. Refer to the Standard PCS and Enhanced PCS architecture chapters for more
details on how these blocks support 1G, 10G protocols and FEC.
Auto Negotiation, IEEE 802.3 Clause 73
The auto negotiation (AN) is needed to synchronize the start time of the link training
on both sides of the link partners. This ensures that the link training can be done
effectively within the 500 ms of the specified time frame as required.
Link Training (LT), IEEE 802.3 Clause 72
Arria 10 devices have soft link training IP that complies with the IEEE 802.3 Clause 72
standard training procedure. This IP includes:
• training frame lock that is different from the regular 64b/66b frame_lock
• training frame generation
• the control channel codec
• Local Device (LD) coefficient update
• Link Partner (LP) coefficient generation
8 + 2
GbE
PCS
1588
FIFO
64 + 8
64 + 8
Auto-Negotiation
Clause 73
Link Training
32
Clause 72
64 + 8
64 + 8
1588
FIFO
8 + 2
GbE
PCS
Hard Logic Unused
Register
Access
Registers
HSSI Reconfiguration
Requests
Native PHY
40/32
Standard TX PCS
tx_pld_clk tx_pma_clk
Enhanced TX PCS
tx_pld_clk tx_pma_clk
Standard RX PCS
rx_pld_clk rx_pma_clk
40/32
Enhanced RX PCS
rx_pld_clk rx_pma_clk
Divide by 33/1/2
® ®
Intel Arria 10 Transceiver PHY User Guide
TX PMA
RX PMA
137