Intel Arria 10 User Manual page 483

Transceiver phy
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5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
Figure 255. 8B/10B Encoder Block Diagrams
When the PCS-PMA Interface Width is 10 bits
To the Serializer
dataout[9:0]
When the PCS-PMA interface width is 10 bits, one 8B/10B encoder is used to convert
the 8-bit data into a 10-bit output. When the PCS-PMA interface width is 20 bits, two
cascaded 8B/10B encoders are used to convert the 16-bit data into a 20-bit output.
The first eight bits (LSByte) is encoded by the first 8B/10B encoder and the next eight
bits (MSByte) is encoded by the second 8B/10B encoder. The running disparity of the
LSByte is calculated first and passed on to the second encoder to calculate the running
disparity of the MSByte.
Note:
You cannot enable the 8B/10B encoder when the PCS-PMA interface width is 8 bits or
16 bits.
5.3.1.3.1. 8B/10B Encoder Control Code Encoding
Figure 256. Control Code Encoding Diagram
tx_parallel_data[15:0]
The
tx_datak
tx_parallel_data
is high, the 8-bit data is encoded as a control word (Kx.y). When
the 8-bit data is encoded as a data word (Dx.y). Depending upon the PCS-PMA
interface width, the width of
interface width is 10 bits,
width is 20 bits,
LSByte of the input data sent to the 8B/10B encoder and the MSB corresponds to the
MSByte of the input data sent to the 8B/10B encoder.
From the Byte Serializer
datain[7:0]
tx_datak
8B/10B Encoder
tx_forcedisp
tx_dispval
tx_clkout
8378
tx_datak[1:0]
0
Code Group
D3.4
D24.3
signal indicates whether the 8-bit data being sent at the
port should be a control word or a data word. When
tx_datak
tx_datak
is a 2-bit word. The LSB of
tx_datak
When the PCS-PMA Interface Width is 20 bits
To the Serializer
8B/10B Encoder
dataout[19:10]
dataout[9:0]
BCBC
0F00
1
D28.5
K28.5
D15.0
is either 1 bit or 2 bits. When the PCS-PMA
is a 1-bit word. When the PCS-PMA interface
tx_datak
®
Intel
Arria
From the Byte Serializer
datain[15:8]
tx_datak[1]
MSB
Encoding
tx_forcedisp[1]
tx_dispval[1]
datain[7:0]
tx_datak[0]
LSB
Encoding
tx_forcedisp[0]
tx_dispval[0]
BF3C
0
D0.0
D31.5
D28.1
tx_datak
is low,
tx_datak
corresponds to the
®
10 Transceiver PHY User Guide
483

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