Intel Arria 10 User Manual page 295

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Enable rx_pma_div_clkout port
rx_pma_div_clkout division factor
Enable rx_pma_clkslip port
Enable rx_pma_qpipulldn port (QPI)
Enable rx_is_lockedtodata port
Enable rx_is_lockedtoref port
Enable rx_set_locktodata and rx_set_locktoref ports
Enable rx_serialpbken port
Enable PRBS verifier control and status ports
Table 214. Enhanced PCS Parameters
Enhanced PCS/PMA interface width
FPGA fabric/Enhanced PCS interface width
Enable Enhanced PCS low latency mode
Enable RX/TX FIFO double width mode
TX FIFO mode
TX FIFO partially full threshold
TX FIFO partially empty threshold
Enable tx_enh_fifo_full port
Enable tx_enh_fifo_pfull port
Enable tx_enh_fifo_empty port
Enable tx_enh_fifo_pempty port
RX FIFO mode
RX FIFO partially full threshold
RX FIFO partially empty threshold
Enable RX FIFO alignment word deletion (Interlaken)
Enable RX FIFO control word deletion (Interlaken)
Enable rx_enh_data_valid port
Enable rx_enh_fifo_full port
Enable rx_enh_fifo_pfull port
Enable rx_enh_fifo_empty port
Enable rx_enh_fifo_pempty port
Parameter
Parameter
Range
On / Off
Disabled, 1, 2, 33, 40, 66
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
Range
32, 40, 64
Note: Basic with KR FEC allows 64 only
32, 40, 50, 64, 66, 67
Note: Basic with KR FEC allows 66 only
On / Off
On / Off
Phase compensation, Register, Interlaken, Basic, Fast
register
Note: Only Basic Enhanced and Basic Enhanced with
KRFEC are valid.
10, 11, 12, 13, 14, 15
1, 2, 3, 4, 5
On / Off
On / Off
On / Off
On / Off
Phase Compensation, Register, Basic
0 to 31
0 to 31
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
® ®
Intel Arria
continued...
10 Transceiver PHY User Guide
295