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4. Resetting Transceiver Channels
UG-01143 | 2018.06.15
a. To ensure successful assertion of
rx_analogreset_ack
the TRS has successfully completed the reset request for assertion.
b. Deassert
2. To ensure successful deassertion of
rx_analogreset_ack
has successfully completed the reset request for deassertion.
3. Wait for
signal goes high after the CDR (automatic lock mode) is locked to data.
4. After
μs). Then deassert
Figure 213. Dynamic Reconfiguration of Receiver Channel During Device Operation
(60)
If the CDR operates in manual lock mode, step
applicable. After
rx_analogreset_ack
Sequence Timing Diagram for Receiver when CDR is in Manual Lock Mode" figure below.
(61)
If the receiver signal detector is enabled and the CDR operates in manual lock mode, step
page 431 and step
wait for
rx_std_signaldetect
continuously for 1 μs or more, apply the reset sequence from the "Reset Sequence Timing
Diagram for Receiver when CDR is in Manual Lock Mode" figure below.
to go high.
rx_analogreset
to go low.
rx_analogreset_ack
rx_is_lockedtodata
rx_digitalreset
Device Power Up
rx_cal_busy
rx_analogreset
rx_analogreset_ack
rx_is_lockedtodata
rx_digitalreset
goes low, apply the reset sequence from the "Reset
4
on page 431 are not applicable. After
to go high. When
rx_analogreset
rx_analogreset_ack
.
rx_analogreset
rx_analogreset_ack
to go low; then ensure
goes high, wait a minimum of t
.
Legal
Reconfiguration
Window
1
2
3
3
on page 431 and step
rx_analogreset_ack
rx_std_signaldetect
®
Intel
, wait for
goes high when
, wait for
goes low when the TRS
(60), (61)
rx_is_lockedtodata
(minimum of 4
LTD
t
min 4 μs
LTD
4
4
on page 431 are not
goes low,
is high
®
Arria
10 Transceiver PHY User Guide
3
on
431
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