Intel Arria 10 User Manual page 486

Depending on your PCS-PMA interface width, the word aligner can be configured in
one of the following modes:
• Bit slip
• Manual alignment
• Synchronous state machine
• Deterministic latency
Figure 259. Word Aligner Conditions and Modes
8 Bit
Bit Slip Manual
Note:
1. This option is available in CPRI mode.
5.3.2.1.1. Word Aligner Bit Slip Mode
In bit slip mode, the word aligner operation is controlled by
to be held for two parallel clock cycles. At every rising edge of
slip circuitry slips one bit into the received data stream, effectively shifting the word
boundary by one bit. Pattern detection is not used in bit slipping mode; therefore,
rx_syncstatus
5.3.2.1.2. Word Aligner Manual Mode
In manual alignment mode, the word aligner operation is controlled by
rx_std_wa_patternalign
sensitive to
width selected.
Table 259.
Word Aligner
PCS-PMA Interface Width
8
10
16
20
If
rx_std_wa_patternalign
programmed word alignment pattern in the received data stream. It updates the word
boundary if it finds the word alignment pattern in a new word boundary. If
rx_std_wa_patternalign
word boundary even when it sees the word alignment pattern in a new word
boundary.
® ®
Intel Arria 10 Transceiver PHY User Guide
486
Single
Width
10 Bit
Bit Slip Deterministic Synchronous
Latency (1) State Machine
is not valid in this mode.
. The word aligner operation is edge-sensitive or level-
rx_std_wa_patternalign
rx_std_wa_patternalign
is asserted, the word aligner looks for the
is deasserted, the word aligner maintains the current
5. Arria 10 Transceiver PHY Architecture
Word
Aligner
Double
Width
16 Bit
Manual Bit Slip Manual Bit Slip
, depending upon the PCS-PMA interface
Behavior
rx_std_wa_patternalign
Rising edge sensitive
Level sensitive
Rising edge sensitive
Rising edge sensitive
UG-01143 | 2018.06.15
20 Bit
Deterministic Synchronous Manual
Latency (1) State Machine
, which has
rx_bitslip
, the bit
rx_bitslip
Behavior