Intel Arria 10 User Manual page 363

3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Parameters
Enable physical output clock
parameters
Enable clklow and fref ports
Desired Reference clock frequency
Actual reference clock frequency
Number of PLL reference clocks
New parameter: Selected reference
clock source
Bandwidth
Operation mode
Multiply factor (M-counter)
Divide factor (N-counter)
Divide factor (L-counter)
Divide factor (K-counter)
PLL output frequency
PLL Datarate
Table 235. fPLL—Master Clock Generation Block Parameters and Settings
Parameters
Include Master Clock Generation
Block
Clock division factor
Enable x6/xN non-bonded high-
speed clock output port
Enable PCIe clock switch interface
(56)
The fPLL and
fref
detection logic.
Range
On/Off
(56)
On/Off
Refer to the GUI
Read-only
1 to 5
0 to 4
Low
Medium
High
Direct
Feedback
compensation
bonding
8 to 127
(integer mode)
11 to 123
(fractional
mode)
1 to 31
1, 2, 4, 8
User defined
Read-only
Read-only
Range
On/Off
1, 2, 4, 8
On/Off
On/Off
signals should only be used with the Intel external soft lock
clklow
Description
This enables the PLL to output frequencies which are not
integral multiples of the input reference clock.
Selecting this option allows you to manually specify M, N, C
and L counter values.
Enables fref and clklow clock ports for external lock
detector. In Transceiver mode when "enable fractional
mode" and "SDI_direct" prot_mode are selected,
pll_locked port is not available and user can create
external lock detector using fref and clklow clock ports.
Specifies the desired PLL input reference clock frequency.
Displays the actual PLL input reference clock frequency.
Specify the number of input reference clocks for the fPLL.
Specifies the initially selected reference clock input to the
fPLL.
Specifies the VCO bandwidth.
Higher bandwidth reduces PLL lock time, at the expense of
decreased jitter rejection.
Specifies the feedback operation mode for the fPLL.
Specifies the multiply factor (M-counter).
Specifies the divide factor (N-counter).
Specifies the divide factor (L-counter).
Specifies the divide factor (K-counter).
Displays the target output frequency for the PLL.
Displays the PLL datarate.
Description
When enabled, includes a master CGB as a part of the fPLL
IP core. The PLL output drives the master CGB.
This is used for x6/xN bonded and non-bonded modes.
Divides the master CGB clock input before generating
bonding clocks.
Enables the master CGB serial clock output port used for
x6/xN non-bonded modes.
Enables the control signals used for PCIe clock switch
circuitry.
® ®
Intel Arria
continued...
10 Transceiver PHY User Guide
363