Intel Arria 10 User Manual page 160

Word Bit R/W
Addr
13 RW
21:16 RW
22 RW
28:24 RW
29 RW
0x4D7
to 0x4FF
2.6.3.6.2. Hard Transceiver PHY Registers
Table 123. Hard Transceiver PHY Registers
Addr Bit Access
0x000-0 [9:0] RW
x3FF
Related Information
Reconfiguration Interface and Dynamic Reconfiguration
2.6.3.6.3. Enhanced PCS Registers
Table 124. Enhanced PCS Registers
Addr Bit
0x480 31:0
0x481 2
3
® ®
Intel Arria 10 Transceiver PHY User Guide
160
Name
LT VODMin ovrd
Enable
LT VPOST ovrd
LT VPOST ovrd Enable
LT VPre ovrd
LT VPre ovrd Enable
Reserved for 40G KR
Name
Access to HSSI
registers
Access Name
RW
Indirect_addr
RW
RCLR_ERRBLK_CNT
RW
RCLR_BER_COUNT
2. Implementing Protocols in Arria 10 Transceivers
Description
When set to 1, enables the override value for the
VODMINRULE parameter stored in the
register field.
Override value for the VPOSTRULE parameter. When
enabled, this value substitutes for the VPOSTRULE to allow
channel-by-channel override of the device settings. This
override only effects the local device TX output for this
channel.
The value to be substituted must be greater than the
INITPOSTVAL parameter for proper operation.
When set to 1, enables the override value for the
VPOSTRULE parameter stored in the
register field.
Override value for the VPRERULE parameter. When enabled,
this value substitutes for the VPOSTRULE to allow channel-
by-channel override of the device settings. This override only
effects the local device TX output for this channel.
The value to be substituted must be greater than the
INITPREVAL parameter for proper operation.
When set to 1, enables the override value for the VPRERULE
parameter stored in the
LT VPre ovrd
Left empty for address compatibility with 40G MAC+PHY KR
solution.
Description
All registers in the physical coding sub-layer (PCS) and physical
media attachment (PMA) that you can dynamically reconfigure
are in this address space. Refer to the Arria 10 Dynamic
Transceiver Reconfiguration chapter for further information.
on page 502
Because the PHY implements a single channel, this
register must remain at the default value of 0 to specify
logical channel 0.
Error block counter clear register. When set to 1, clears
the
RCLR_ERRBLK_CNT
operation continues.
BER counter clear register. When set to 1, clears the
register. When set to 0, normal
RCLR_BER_COUNT
operation continues.
UG-01143 | 2018.06.15
LT VODMin ovrd
LT VPOST ovrd
register field.
Description
register. When set to 0, normal
continued...