Intel Arria 10 User Manual page 217

Transceiver phy

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2. Implementing Protocols in Arria 10 Transceivers

UG-01143 | 2018.06.15

Implementation of the XGMII Specification in Arria 10 Devices Configuration

The ATX PLL is only supported to drive the internal transceiver. The FPLL is only supported to drive

xgmii_tx_clk

clock to maintain 0 ppm.

Interface Clock (156.25 MHz)

8B/10B Encoding/Decoding

Each of the four lanes in a XAUI configuration supports an independent 8B/10B

encoder/decoder as specified in Clause 48 of the IEEE802.3-2008 specification.

8B/10B encoding limits the maximum number of consecutive 1s and 0s in the serial

data stream to five. This limit ensures DC balance as well as enough transitions for the

receiver CDR to maintain a lock to the incoming data.

The XAUI PHY IP core provides status signals to indicate both running disparity and

the 8B/10B code group error.

. Both the ATX PLL and the FPLL must be clocked by the same reference

xgmii_rx_clk

XGMII Transfer (DDR)

Arria 10 Soft PCS Interface (SDR)

10 Transceiver PHY User Guide

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