Intel Arria 10 User Manual page 150

Word Bit R/W
Addr
7:4 RW
8 RW
11:9 RW
12 RW
16 RW
17 RW
18 RW
0x4B1 0 R
1 R
2 R
13:8 R
16 R
17 R
0x4B2 0:10 —
11 RW
® ®
Intel Arria 10 Transceiver PHY User Guide
150
Name
Forces the sequencer to a specific protocol. Must write the
SEQ Force Mode[3:0]
Reset SEQ
encodings are defined:
•
•
•
•
•
•
When set to 1, it enables the Arria 10 HSSI reconfiguration
Enable Arria 10
calibration as part of the PCS dynamic reconfiguration. 0 skips
Calibration
the calibration when the PCS is reconfigured.
Reserved —
When set to 1, LT failure causes the PHY to go into data
LT failure response
mode. When set to 0, LT failure restarts auto-negotiation (if
enabled). If auto-negotiation is not enabled, the PHY restarts
LT.
When set to 1, FEC is enabled. When set to 0, FEC is
KR FEC enable 171.0
disabled. Resets to the CAPABLE_FEC parameter value.
When set to 1, KR PHY FEC decoding errors are signaled to
KR FEC enable err
the PCS. When set to 0, FEC errors are not signaled to the
ind 171.1
PCS. See Clause 74.8.3 of IEEE 802.3ap-2007 for details.
When set to 1, enables the FEC request. When this bit
KR FEC request
changes, you must assert the
renegotiate with the new value. When set to 0, disables the
FEC request.
When asserted, the sequencer is indicating that the link is
SEQ Link Ready
ready.
When asserted, the sequencer has had an Auto Negotiation
SEQ AN timeout
timeout. This bit is latched and is reset when the sequencer
restarts Auto Negotiation.
When set, indicates that the Sequencer has had a timeout.
SEQ LT timeout
Specifies the Sequencer mode for PCS reconfiguration. The
SEQ Reconfig
following modes are defined:
Mode[5:0]
•
•
•
•
•
•
When set to 1, indicates that the 10GBASE-KR PHY supports
KR FEC ability 170.0
FEC. Set as parameter
refer to Clause 45.2.1.84 of IEEE 802.3ap-2007.
When set to 1, indicates that the 10GBASE-KR PHY is capable
KR FEC err ind
of reporting FEC decoding errors to the PCS. For more
ability 170.0
information, refer to Clause 74.8.3 of IEEE 802.3ap-2007.
Reserved —
Writing a 1 inserts one error pulse into the TX FEC depending
KR FEC TX Error
on the Transcoder and Burst error settings. This bit self
Insert
clears.
2. Implementing Protocols in Arria 10 Transceivers
Description
bit to 1 for the Force to take effect. The following
0000: No force
0001: GigE
0010: XAUI
0100: 10GBASE-R
0101: 10GBASE-KR
1100: 10GBASE-KR FEC
Reset SEQ
Bit 8, mode[0]: AN mode
Bit 9, mode[1]: LT Mode
Bit 10, mode[2]: 10G data mode
Bit 11, mode[3]: GigE data mode
Bit 12, mode[4]: Reserved for XAUI
Bit 13, mode[5]: 10G FEC mode
SYNTH_FEC
UG-01143 | 2018.06.15
bit (0x4B0[0]) to
. For more information,
continued...