Intel Arria 10 User Manual page 157

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Word Bit R/W
Addr
0x4D3 9:0 RW
19:10 RW
29:20 RW
0x4D4 5:0 RO or
RW
6 RO or
RW
7 RO or
RW
0x4D4 13:8 RO
Name
Specifies the number of training frames to examine for bit
ber_time_frames
errors on the link for each step of the equalization settings.
Used only when ber_time_k_frames is 0.The following values
are defined:
•
•
•
The default value for simulation is 2'b11. The default value for
hardware is 0.
Specifies the number of thousands of training frames to
ber_time_k_frames
examine for bit errors on the link for each step of the
equalization settings. Set ber_time_m_frames = 0 for time/
bits to match the following values:
•
•
•
The default value for simulation is 0. The default value for
hardware is 0xF.
Specifies the number of millions of training frames to examine
ber_time_m_frames
for bit errors on the link for each step of the equalization
settings. Set ber_time_k_frames = 4'd1000 = 0x43E8 for
time/bits to match the following values:
•
•
•
Reflects the contents of the first 16-bit word of the training
LD coefficient
frame sent from the local device control channel. Normally,
update[5:0]
the bits in this register are read-only; however, when you
override training by setting the
control bit, these bits become writable. The following fields
are defined:
•
•
•
For more information, refer to 10G BASE-KR LD coefficient
update register bits (1.154.5:0) in Clause 45.2.1.80.3 of IEEE
802.3ap-2007.
When set to 1, requests the link partner coefficients be set to
LD Initialize
configure the TX equalizer to its INITIALIZE state. When set
Coefficients
to 0, continues normal operation. For more information, refer
to 10G BASE-KR LD coefficient update register bits (1.154.12)
in Clause 45.2.1.80.3 and Clause 72.6.10.2.3.2 of IEEE
802.3ap-2007.
When set to 1, requests the link partner coefficients be set to
LD Preset
a state where equalization is turned off. When set to 0 the
Coefficients
link operates normally. For more information, refer to 10G
BASE-KR LD coefficient update register bit (1.154.13) in
Clause 45.2.1.80.3 and Clause 72.6.10.2.3.2 of IEEE
802.3ap-2007.
Status report register for the contents of the second, 16-bit
LD coefficient
word of the training frame most recently sent from the local
status[5:0]
device control channel. The following fields are defined:
Description
3
A value of 2 is about 10 bytes
4
A value of 20 is about 10 bytes
5
A value of 200 is about 10 bytes
7
A value of 3 is about 10 bits = about 1.3 ms
8
A value of 25 is about 10 bits = about 11ms
9
A value of 250 is about 10 bits = about 11 0ms
10
A value of 3 is about 10 bits = about 1.3 seconds
11
A value of 25 is about 10 bits = about 11 seconds
12
A value of 250 is about 10 bits = about 110 seconds
Ovride Coef enable
[5: 4]: Coefficient (+1) update
— 2'b11: Reserved
— 2'b01: Increment
— 2'b10: Decrement
— 2'b00: Hold
[3:2]: Coefficient (0) update (same encoding as [5:4])
[1:0]: Coefficient (-1) update (same encoding as [5:4])
® ®
Intel Arria
continued...
10 Transceiver PHY User Guide
157