Intel Arria 10 User Manual page 138

Reconfiguration Block
The Reconfiguration Block performs Avalon-MM writes to the PHY for both PCS and
PMA reconfiguration. The Avalon-MM master accepts requests from the PMA or PCS
controller. It performs the Read-Modify-Write or Write commands on the Avalon-MM
interface. The PCS controller receives rate change requests from the Sequencer and
translates them to a series of Read-Modify-Write or Write commands to the PMA and
PCS.
Eight compile-time configuration modes are supported. The configuration modes
include one set of four with reference clock at 322 MHz and one set of four with
reference clock at 644 MHz. Each set of four consists of all combinations of FEC
sublayer on/off.
Figure 69. Reconfiguration Block Details
MGMT_CLK
Reconfiguration
Interface
Reconfiguration
Interface
Notes:
1. rcfg = Reconfiguration
2. MGMT_CLK = Management Clock
Related Information
• Arria 10 Enhanced PCS Architecture
• Arria 10 Standard PCS Architecture
2.6.3.4. Parameterizing the 10GBASE-KR PHY
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter
values.
The Arria 10 1G/10GbE and 10GBASE-KR PHY IP core allows you to select either the
Backplane-KR or 1Gb/10Gb Ethernet variant. When you select the Backplane-KR
variant, the Link Training (LT) and Auto Negotiation (AN) tabs appear. The 1Gb/
10Gb Ethernet variant (1G/10GbE) does not implement the LT and AN functions.
Complete the following steps to parameterize the 10GBASE-KR PHY IP core in the
parameter editor:
1. Instantiate the Arria 10 1G/10GbE and 10GBASE-KR PHY from the IP Catalog.
® ®
Intel Arria 10 Transceiver PHY User Guide
138
(2)
PCS
PCS
Controller
PMA Controller
TX EQ Controller
DFE Controller
PMA
CTLE Controller
2. Implementing Protocols in Arria 10 Transceivers
rcfg_data
rcfg_data
rcfg_data
Avalon-MM Bus
rcfg_data
(1)
Avalon-MM Bus
Avalon-MM Bus
Avalon-MM reconfig_busy Signal
on page 461
on page 479
UG-01143 | 2018.06.15
Avalon-MM
HSSI
Decoder
Reconfiguration
Requests