Intel Arria 10 User Manual page 308

The following figure shows the deletion of D5 when the upstream transmitter
reference clock frequency is greater than the local receiver reference clock
frequency. It asserts
deletion takes place.
Figure 146. Rate Match FIFO Becoming Full After Receiving D5
rx_std_rmfifo_full
The following figure shows the insertion of skip symbols when the local receiver
reference clock frequency is greater than the upstream transmitter reference clock
frequency. It asserts
the insertion takes place.
Figure 147. Rate Match FIFO Becoming Empty After Receiving D3
tx_parallel_data
rx_parallel_data
rx_std_rmfifo_empty
2.9.2.8. Rate Match FIFO Basic (Double Width) Mode
1. Select basic (double width) in the RX rate match FIFO mode list.
2. Enter values for the following parameters.
Parameter
RX rate match insert/delete +ve
pattern (hex)
RX rate match insert/delete -ve
pattern (hex)
The rate match FIFO can delete as many pairs of skip patterns from a cluster as
necessary to avoid the rate match FIFO from overflowing. The rate match FIFO
can delete a pair of skip patterns only if the two 10-bit skip patterns appear in the
same clock cycle on the LSByte and MSByte of the 20-bit word. If the two skip
patterns appear straddled on the MSByte of a clock cycle and the LSByte of the
next clock cycle, the rate match FIFO cannot delete the pair of skip patterns.
In the following figure, the first skip cluster has a /K28.5/ control pattern in the
LSByte and /K28.0/ skip pattern in the MSByte of a clock cycle followed by one /
K28.0/ skip pattern in the LSByte of the next clock cycle. The rate match FIFO
cannot delete the two skip patterns in this skip cluster because they do not appear
in the same clock cycle. The second skip cluster has a /K28.5/ control pattern in
the MSByte of a clock cycle followed by two pairs of /K28.0/ skip patterns in the
next two cycles. The rate match FIFO deletes both pairs of /K28.0/ skip patterns
(for a total of four skip patterns deleted) from the second skip cluster to meet the
three skip pattern deletion requirement.
® ®
Intel Arria 10 Transceiver PHY User Guide
308
rx_std_rmfifo_full
tx_parallel_data D1 D2
rx_parallel_data D1 D2
rx_std_rmfifo_empty
D1
D1
Value
20 bits of data specified
as a hexadecimal string
20 bits of data specified
as a hexadecimal string
2. Implementing Protocols in Arria 10 Transceivers
for one parallel clock cycle while the
D3 D4 D5 D6
D7
D3 D4 D6
for one parallel clock cycle while
D2 D3
D2 D3
The first 10 bits correspond to the skip pattern and the
last 10 bits correspond to the control pattern. The skip
pattern must have neutral disparity.
The first 10 bits correspond to the skip pattern and the
last 10 bits correspond to the control pattern. The skip
pattern must have neutral disparity.
UG-01143 | 2018.06.15
D7 D8
D8 xx xx xx
D4 D5
/K30.7/ D4
Description
D6
D5