Intel Arria 10 User Manual page 98

Transceiver phy

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10X12.5 Gbps xN Bonding

Related Information

Implementing x6/xN Bonding Mode

For detailed information on xN bonding limitations

Using PLLs and Clock Networks

For more information about implementing PLLs and clocks

2.5.2.2. TX Multi-Lane Bonding and RX Multi-Lane Deskew Alignment State

The Interlaken configuration sets the enhanced PCS TX and RX FIFOs in Interlaken

elastic buffer mode. In this mode of operation, TX and RX FIFO control and status port

signals are provided to the FPGA fabric. Connect these signals to the MAC layer as

required by the protocol. Based on these FIFO status and control signals, you can

implement the multi-lane deskew alignment state machine in the FPGA fabric to

control the transceiver RX FIFO block.

You must also implement the soft bonding logic to control the transceiver TX FIFO

10 Transceiver PHY User Guide

Transceiver PLL

Instance (6.25 GHz)

2. Implementing Protocols in Arria 10 Transceivers

Native PHY Instance

(10 Ch Bonded 12.5 Gbps)

Transceiver Bank 1

Transceiver Bank 2

UG-01143 | 2018.06.15

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