Intel Arria 10 User Manual page 440

Signal Name
rx_analogreset
[<n>-1:0]
rx_ready[<n>-1:0]
pll_powerdown[<p>-1:0
]
Usage Examples for
•
If a single channel can switch between three TX PLLs, the
indicates which one of the selected three TX PLL's
communicate the PLL lock status to the TX reset sequence. In this case, to select
the 3-bits wide
• If three channels are instantiated with three TX PLLs and with a separate TX reset
sequence per channel, the
In this case,
represents channel 1, and
channel, a separate
• If three channels are instantiated with three TX PLLs and with a single TX reset
sequence for all three channels, then
case, the same
channels.
•
If one channel is instantiated with one TX PLL,
Connect
• If three channels are instantiated with only one TX PLL and with a separate TX
reset sequence per channel, the
pll_select
® ®
Intel Arria 10 Transceiver PHY User Guide
440
Direction Clock Domain
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
pll_select
port, the
pll_locked
pll_select
pll_select [1:0]
pll_select[5:4]
pll_locked
signal indicates the PLL lock status for all three
pll_locked
to logic 0.
pll_select
should be set to 0 since there is only one TX PLL available.
4. Resetting Transceiver Channels
Description
•
is asserted
reset
•
rx_analogreset
•
is asserted
rx_cal_busy
•
rx_is_lockedtodata
is deasserted
rx_manual
When all of these conditions are false, the reset
counter begins its countdown for deassertion of
.
rx_digitalreset
Analog reset for RX. When asserted, resets the RX CDR
and the RX PMA blocks of the transceiver PHY. This
signal is asserted when any of the following conditions
is true:
•
is asserted
reset
•
is asserted
rx_cal_busy
The width of this signal depends on the number of
channels.
Status signal to indicate when the RX reset sequence is
complete. This signal is deasserted while the RX reset
is active. It is asserted a few clock cycles after the
deassertion of
rx_digitalreset
implementations may require you to monitor this signal
prior to sending data. The width of this signal depends
on the number of RX channels.
Asserted to power down a transceiver PLL circuit. When
asserted, the selected TX PLL is reset.
pll_locked
port is 2-bits wide.
pll_select
field is 6-bits wide (2-bits per channel).
represents channel 0,
represents channel 2. For each
signal indicates the PLL lock status.
field is 2-bits wide. In this
pll_select
pll_select
field is 3-bits wide. In this case,
pll_select
UG-01143 | 2018.06.15
is asserted
is deasserted and
. Some protocol
signal
pll_select
signal is used to
pll_select[3:2]
field is 1-bit wide.