Intel Arria 10 User Manual page 561

6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
When performing a dynamic reconfiguration, you must:
• Include constraints to create the extra clocks for all modified or target
configurations at the PCS-FPGA fabric interface. Clocks for the base configuration
are created by the Quartus Prime software. These clocks enable the Quartus Prime
software to perform static timing analysis for all the transceiver configurations and
their corresponding FPGA fabric core logic blocks.
• Include the necessary false paths between the PCS – FPGA fabric interface and the
core logic.
For example, you can perform dynamic reconfiguration to switch the datapath from
Standard PCS to Enhanced PCS using the multiple reconfiguration profiles feature. In
the following example, the base configuration uses the Standard PCS (data rate =
1.25 Gbps, PCS-PMA width = 10) and drives core logic A in the FPGA fabric. The target
or modified configuration is configured to use the Enhanced PCS (data rate = 12.5
Gbps, PCS-PMA width = 64) and drives core logic B in the FPGA fabric.
Figure 280. Using Multiple Reconfiguration Profiles
FPGA Fabric
tx_clkout
Core Logic (A)
for Standard
PCS
Core Logic (B)
for Enhanced
rx_clkout
PCS
Transceiver Channel
Transmitter (TX)
Receiver (RX)
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Intel Arria 10 Transceiver PHY User Guide
561