Intel Arria 10 User Manual page 192

2.6.4.7.3. Enhanced PCS Registers
Table 147. Enhanced PCS Registers
Addr Bit
0x480 31:0
0x481 2
3
0x482 1
2
3
4
7
2.6.4.7.4. Arria 10 GMII PCS Registers
Addr Bit R/W
0x490 9 RW
12 RW
15 RW
0x491 2 R
3 R
5 R
0x494 5 RW
(1000BASE-
X mode)
6 RW
® ®
Intel Arria 10 Transceiver PHY User Guide
192
Access Name
RW
Indirect_addr
RW
RCLR_ERRBLK_CNT
RW
RCLR_BER_COUNT
RO
HI_BER
RO
BLOCK_LOCK
RO
TX_FIFO_FULL
RO
RX_FIFO_FULL
RO
Rx_DATA_READY
Name
RESTART_AUTO_ NEGOTIATION
AUTO_NEGOTIATION_ ENABLE
Reset
LINK_STATUS
AUTO_NEGOTIATION_ ABILITY
AUTO_NEGOTIATION_ COMPLETE
FD
HD
2. Implementing Protocols in Arria 10 Transceivers
Description
Because the PHY implements a single channel, this
register must remain at the default value of 0 to specify
logical channel 0.
Error block counter clear register. When set to 1, clears
the register. When set to 0, normal
RCLR_ERRBLK_CNT
operation continues.
BER counter clear register. When set to 1, clears the
register. When set to 0, normal
RCLR_BER_COUNT
operation continues.
High BER status. When set to 1, the PCS reports a high
BER. When set to 0, the PCS does not report a high
BER.
Block lock status. When set to 1, the PCS is locked to
received blocks. When set to 0, the PCS is not locked to
received blocks.
When set to 1, the is full.
TX_FIFO
When set to 1, the is full.
RX_FIFO
When set to 1, indicates the PHY is ready to receive
data.
Description
Set this bit to 1 to restart the Clause 37 auto-
negotiation (AN) sequence. For normal operation, set
this bit to the default 0 value. This bit is self-clearing.
Set this bit to 1 to enable Clause 37 AN. The default
value is 1.
Set this bit to 1 to generate a synchronous reset pulse
which resets all the PCS state machines, comma
detection function, and the 8B/10B encoder and
decoder. For normal operation, set this bit to 0. This
bit self clears.
A value of 1 indicates that a valid link is operating. A
value of 0 indicates an invalid link. If link
synchronization is lost, this bit is 0.
A value of 1 indicates that the PCS function supports
Clause 37 AN.
A value of 1 indicates the following status:
• The AN process is complete.
• The AN control registers are valid.
Full-duplex mode enable for the local device. Set to 1
for full-duplex support.
Half-duplex mode enable for the local device. Set to 1
for half-duplex support. This bit should always be set
to 0 for the KR PHY IP.
UG-01143 | 2018.06.15
continued...