Intel Arria 10 User Manual page 356

Parameter
Clock division factor
Enable x6/xN non-bonded high-
speed clock output port
Enable PCIe clock switch interface
Number of auxiliary MCGB clock
input ports
MCGB input clock frequency
MCGB output data rate.
Enable bonding clock output ports
Enable feedback compensation
bonding
PMA interface width
Table 231. ATX PLL—Dynamic Reconfiguration
Parameter
Enable reconfiguration
Enable Altera Debug Master
Endpoint
Separate reconfig_waitrequest
from the status of AVMM
arbitration with PreSICE
Enable capability registers
Set user-defined IP identifier
Enable control and status registers
Configuration file prefix
® ®
Intel Arria 10 Transceiver PHY User Guide
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Range
This is used for x6/xN bonded and non-bonded modes.
1, 2, 4, 8 Divides the master CGB clock input before generating
bonding clocks.
On/Off Enables the master CGB serial clock output port used for
x6/xN non-bonded modes.
On/Off Enables the control signals for the PCIe clock switch
circuitry. Used for PCIe clock rate switching.
0, 1 Auxiliary input is used to implement the PCIe Gen3
protocol.
Read only Displays the master CGB's input clock frequency.
Read only Displays the master CGB's output data rate.
On/Off
Enables the
master CGB used for channel bonding.
This option should be turned ON for bonded designs.
On/Off Enables this setting when using feedback compensation
bonding. For more details about feedback compensation
bonding, refer to the PLL Feedback Compensation Bonding
section later in the document.
8, 10, 16, 20, Specifies PMA-PCS interface width.
32, 40, 64
Match this value with the PMA interface width selected for
the Native PHY IP core. You must select a proper value for
generating bonding clocks for the Native PHY IP core.
Range
On/Off Enables the PLL reconfiguration interface. Enables the
simulation models and adds Avalon compliant ports for
reconfiguration.
On/Off When you turn on this option, the Transceiver PLL IP core
includes an embedded Altera Debug Master Endpoint
(ADME) that connects internally to the Avalon-MM slave
interface for dynamic reconfiguration. The ADME can access
the reconfiguration space of the transceiver. It can perform
certain test and debug functions via JTAG using the System
Console. Refer to the Reconfiguration Interface and
Dynamic Reconfiguration chapter for more details.
On/Off
When enabled, the
indicate the status of AVMM arbitration with PreSICE. The
AVMM arbitration status is reflected in a soft status register
bit. (Only available if "Enable control and status registers
feature" is enabled).
On/Off Enables capability registers that provide high-level
information about the ATX PLL's configuration.
User-defined Sets a user-defined numeric identifier that can be read from
the
user_identifier
are enabled.
On/Off Enables soft registers for reading status signals and writing
control signals on the PLL interface through the embedded
debug logic.
Enter the prefix name for the configuration files to be
generated.
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Description
output ports of the
tx_bonding_clocks
Description
reconfig_waitrequest
offset when the capability registers
does not
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